0
votes

Now, I'm trying to use clocking statement in systemverilog as following.

interface itf();
...

clocking cb @(posedge clk); 
default input #3ns output #5ns; 

output read,enable,addr; 
input negedge data; 
endclocking 

...
endinterface

As I think, above code that are using output and input have delay. read,enable,addr have 5ns delay, and data is delayed 3ns. but It does not work well. would you please give any advice? If you can, Would you show me example code with that codes?

I want to see that works which input #3ns and output #5ns Thanks.

update1

module top();
logic clk;
initial begin
clk =0;
forever #5 clk= ~clk;
end
itf u_itf(.clk(clk));
dut u_dut(u_itf);
tb_u_tb(u_itf);
endmodule

module tb (itf tb);
initial begin
tb.read <= 0;
repeat(3) #10 tb.read <= ~tb.read;
$finish;
end

always @(posedge tb.clk) begin
tb.cb.read <=tb.cb;
if (tb.cb.enable)
tb.data  <= tb.data+1;
end

initial begin 
tb.data =0;
end

endmodule

module dut(itf dut_itf);
always  @(posedge dut_itf.clk) begin
if (dut_itf.read)
dut_itf.enable <= 1;
end

initial begin 
dut_itf.enable <= 0;
end
endmodule

interface itf(input clk);
logic read,enable;
logic [7:0]  addr, data;
modport dut(input read, addr, output data, enable);
modport tb(clocking cb);

clocking cb@(posedge clk);
default input #3ns //output #5ns; //Here is my test point.
output data, addr, read;
input enable;
endclocking


endinterface

As you can see the code, I want to test about the "default input #3ns output #5ns;" and "default input #3ns //output #5ns;"

But default input #3ns //output #5ns; does not work.

Also How can we proving the tb.read value?

update2.

Should I have to modity like as following?

 module tb (itf tb);
 initial begin 
 tb.cb.read <= 0; 
 repeat(3) tb.cb.read <= ~tb.cb.read;
 $finish;
 end 
 always @( tb.cb) begin
 tb.cb.read <=tb.cb; 
 if (tb.cb.enable)
 tb.cb.data <= tb.cb.data+1; 
 end 
 initial begin 
 tb.cb.data =0; 
 end endmodule 

update 3

I got it the idea about clocking statement. But I want to know what kind of event use the input of clocking . What kind of examples are used in the input of clocking?

1
Please explain what you mean by "but it does not work well". - dave_59
@dave_59 : I'm not sure fully I understand clocking statement in systemverilog, but as I know if we use clocking statement in interface, then that default delay does affect to timing. Especially, the input that what if we use the input 3ns for example, then the input signal has delayed by 3ns. But my simulation does not affected. BTW, what if I use output 5ns then that ouput signals are all affected by 5ns delay. So I need example code about fully be able to use clocking statement. - bural

1 Answers

0
votes

There are many clocking block examples you can find if you search. Here's one. Some of the problems I see with your code is that you are that you are making simultaneous assignments to the read signal with a non-blocking assignment directly and a clocking block drive statement from the testbench. A general rule for using clocking blocks is defined for an interface, the clocking block signals are the only signals you should be interacting with. That includes the event controls for synchronization. You should not be using #10 or @(posedge tb.clk) - just use @(tb.cb).