How to use wildcard string in systemverilog case statement

Question

Case #1:

module try;
  string inp = "my_var";

  initial begin
    $display("Here we go!");
    case (inp) 
    "my_var" : $display("my_var");
    default : $display("default");
    endcase
  end
endmodule

Output is my_var

Case #2

module try;
  string inp = "my_var";

  initial begin
    $display("Here we go!");
    case (inp) 
    "*var*" : $display("*var*");
    default : $display("default");
    endcase
  end
endmodule

Output is default.

Is it possible to get a hit with wildcard search in a case statement?

Answer 1

SystemVerilog does not have any string regular expression matching methods built into the standard. The UVM has a package that has a uvm_re_match() function. You can import the UVM package to get access to this function even if you do not use any other UVM testbench features. Some simulators, such as ModelSim/Questa have these routines built in as an extension to SystemVerilog so that you can do

module try;
  string inp = "my_var";

  initial begin
    $display("Here we go!");
    case (1) 
      inp.match("*var*") : $display("*var*");
      default            : $display("default");
    endcase
  end
endmodule

Answer 2

I found a work-around :

function string match(string s1,s2); 
int l1,l2; 
l1 = s1.len(); 
l2 = s2.len(); 
match = 0 ; 
if( l2 > l1 ) 
return 0; 
for(int i = 0;i < l1 - l2 + 1; i ++) 
if( s1.substr(i,i+l2 -1) == s2) 
return s2; 
endfunction 

module try;
  string target_id = "abc.def.ddr4_0";
  string inp     = "ddr4_0";
  string processed_inp;

  initial begin
    $display("Here we go!");
    for(int i=0;i<2;i++) begin
      if (i == 1)begin
        inp     = "ddr4_1";
        target_id = "abc.def.ddr4_1";
      end
      processed_inp = match(target_id, inp);
      $display("input to case = %0s", processed_inp);
      case (processed_inp) 
      "ddr4_0"   : $display("ddr4_0 captured!");
      "ddr4_1"   : $display("ddr4_1 captured!");
      default : $display("default");
      endcase
    end
  end
endmodule

Output:

Here we go!
input to case = ddr4_0
ddr4_0 captured!
input to case = ddr4_1
ddr4_1 captured!

PS : Found this solution on the www. Cannot find the link right now. Will post the reference soon.