How does SystemVerilog handle possible wildcard conflicts in case statements?

Question

When I write a case statement that includes wildcards for the cases, how are more or less specific cases handled?

always_comb case(selector)
    4'b0???: begin // Pick me if the msb is 0, unless the two lsb's are 01.
    end
    4'b0?01: begin // Pick me if the msb is 0 and the two lsb's are 01.
    end
    default: begin // Pick me if the msb is X or 1.
    end
endcase

In the simplified example above, the first case (all wildcards) could be selected for any value of selector, but I want it to select the most specific possible case. Is that how cases are handled?

cases are always priority based and once a case statement is matched, all the statement below that case won't be executed. — Karan Shah

dave_59 dave_59 · Accepted Answer · 2017-03-17T22:22:36

SystemVerilog assumes the case statement is in priority order - the second item is never matched. So you need to move the most specific cases first. SystemVerilog has unique case and priority case constructs to better specify your intent.

How does SystemVerilog handle possible wildcard conflicts in case statements?

1 Answers