SystemVerilog wait() statement

Question

Is the following code is supported in SystemVerilog?

int cnt = 0;
wait( cnt == (cnt+1) )

Could any one point me the section in LRM?

Answer 1

This is supported. But the main question is, what will you get by such wait statement, as this statement will never be evaluated as "true".

May be I can help you, if you provide more details on, what you exactly want to do through this wait statement.

Meanwhile, here is the code, as per your wait statement, with it's output. This will help you to understand, what this wait statement will do:

// Sample code, as per your wait statement
module top();
  int cnt;
  bit clk;

  always #5 clk = ~clk;

  always @ (posedge clk)
    cnt <= cnt + 1;

  initial
    begin
      $display("***** Before wait *****");
      wait(cnt == (cnt + 1))
      $display("***** After wait *****");
    end

  initial #100 $finish;
  initial $monitor("cnt - %0d", cnt);    
endmodule

// Output of this sample code
***** Before wait *****
cnt - 0
cnt - 1
cnt - 2
cnt - 3
cnt - 4
cnt - 5
cnt - 6
cnt - 7
cnt - 8
cnt - 9
cnt - 10
$finish called from file "testbench.sv", line 20.
$finish at simulation time                  100

Answer 2

I guess the answer depends on what you mean by supported? You are certainly allowed to write expressions that make no sense and would always result in false (1'b0). That would cause the wait statement to hang and suspend whatever process executed it.

Answer 3

Yes it is supported. You would not get any compilation error even if logically you know it is going to hang. (If that was your intention while asking)

"wait" statement is level sensitive and will wait infinitely till the expression is evaluated to be true. It is usually used to wait for an event before executing another event or to delay the execution of the code till some event has occurred.

Since in systemverilog the threads are created dynamically, synchronization between events is necessary and that is where wait statements can be used.

LRM section where you can read more about wait statement: 9.4.3 (Level sensitive event control)

Answer 4

Instead of the uvm_event you could use SystemVerilog's own event type. This removes the dependency to the uvm_pkg.

class container;
  event from_a;

  task a();
    ...
    -> from_a;
    ...
  endtask

  task b();
    ...
    @ from_a;
    ...
  endtask
endclass

You can find a lot about interprocess communication (mailbox, semaphore, mutex, events) @ LRM Chapter 15.