System Verilog Clocking block

Question

I am trying to perform a simple test with demo code of Clocking block, but encountered the error.

The code could be find at "EDA playground" http://www.edaplayground.com/x/3Ga

And the error says: ** Error: testbench.sv(38): A default clocking block must be specified to use the ##n timing statement. ** Error: testbench.sv(40): A default clocking block must be specified to use the ##n timing statement.

I think the clocking block has already been specified in the code.

Any Help?

Answer 1

As the error message says, you have to define the clocking block as default:

default clocking cb_counter @(posedge Clock);

Full code here: http://www.edaplayground.com/x/37_

The SV 2012 standard specifies that the ##n operator can only be used if there is a default clocking block defined for the module/program/interface, otherwise it wouldn't be able to know what clock event to use for the delay.

Answer 2

##N delays are not a very useful feature unless you can put them in the same module or interface that the clocking block is defined in. That is typically not the case because you usually put your driver code inside a class inside a package.

repeat (N) @cb_counter;

This works uniformly, even if referencing the cb through a virtual interface.

Answer 3

To resolve the error add default clocking cb_counter; after your clocking block.

SystemVerilog IEEE1800-2012 Section 14 Covers Clocking Blocks.

// Test program
program test_counter;
  // SystemVerilog "clocking block"
  // Clocking outputs are DUT inputs and vice versa
  clocking cb_counter @(posedge Clock);
    default input #1step output #4;
    output negedge Reset;
    output Enable, Load, UpDn, Data;
    input Q;
  endclocking
  default clocking cb_counter;    //<-- Set default clocking

  // Apply the test stimulus
  initial begin
  //..

Below I have included a my method of creating a testbench clock, with the initial it is easy to work out when it will be triggered, compared to the original always the time for the first trigger my vary depending on how when the Clk is initialised.

initial begin
  Clk = 0;
  forever begin
    #5ns Clk = ~Clk;
  end
end

If you simulator allows system-verilog, I would use #5ns so that it does not rely on the timestep, I find this to more readable and reliable for code reuse.

The version from the question, used an always block.

  timeunit 1ns;
  // Clock generator
  always
  begin
    #5 Clock = 1;
    #5 Clock = 0;
  end