assignment under multiple single edges is not supported for synthesis , change it to warning

Question

I have Code below which is written in verilog.
The problem is, I want to change a reg named PC inside an always block I need to handle this in multiple Always Block. If I do that, I get multiple drive error which make sense.
So I tried to add some other variables in sensitivity list but I get this error:

assignment under multiple single edges is not supported for synthesis.

I cant change the structure of code. please give me a solution the code:

always@( posedge clk or posedge PC_SRC or posedge PC_Jmp)
begin
        if( clk == 1   )
        begin
            PC = PC + 1 ; 
        end

        if(  PC_SRC == 1  )
        begin
            PC = PC + Branch_PC ; 
        end

        if( PC_Jmp == 1)
        begin
            PC = Branch_PC ;  
        end
end

Greg Greg · Accepted Answer · 2015-11-06T20:54:31

With synchronous design, you can have one edge triggered clocking signal. Depending on your synthesize library, one or two asynchronous control pins (posedge gets mapped to active high, negedge gets mapped to active low). Asynchronous control pins are identified by the synthesizer by being used used within the always block, and can be for assigning variables to constants. Note you should never reference the synchronous clocking signal in the always block.

To be synthesizable, a reg can only be assigned within one always block.

Synchronous assignments should be made with non-blocking assignments (<=), not blocking assignments (=). Use blocking assignments in combinational blocks (always @*). Using the appropriate assignment types will prevent RTL simulation race conditions and simulation RTL-vs-gate behavioral differences.

Your code should look something like this:

always @( posedge clk )
begin
    if ( PC_Jmp == 1 )
    begin
        PC <= Branch_PC ;  
    end
    else if ( PC_SRC == 1 )
    begin
        PC <= PC + Branch_PC ; 
    end
    else
    begin
        PC <= PC + 1 ; 
    end
end

assignment under multiple single edges is not supported for synthesis , change it to warning

2 Answers