stuck in while loop verilog

Question

I seem to have written myself into an infinite loop, either that or that Modelsim does not know what to do with the conditions in this while loop:

i = 0;
while(i < 8'b01100100 && !(mem[i] == RC)) begin
   i <= i + 1;
end

simulation just cannot get past the conditional line in this while loop, can anyone point to what I am doing wrong?

-edit: the part of the code that holds the while loop:

//if remove credential enable is high
if(RCE == 1'b1) begin
  $display ("%d", RC);
  $display ("%d", mem[i]);
  $display ("%b", !(mem[i] == RC));
    while(i < 8'b01100100 && mem[i] != RC) begin
      i <= i + 1;
    end
    if(i < 8'b01100100) begin
        mem[i] <= 24'b111111111111111111111111;
    end else begin
        //do nothing
    end
    i = 0;
    end else begin
        //do nothing
    end

this part is inside of an always block with the sensitivity list of posedge clk and posedge rst.

How many bits is i? Can you post the whole file if it's not too large? — Tim
i is 8 bits wide, the whole code is 194 lines long... if you need more of the code, I am more than happy do oblige — user1475941
There is a line with i = 0; is this meant to be there. For synthesis you should be able to unroll your loops, I do not see how this would work in your current code. — Morgan

Andy Andy · Accepted Answer · 2012-12-12T03:41:40

You need to use a blocking assignment rather than a non-blocking assignment in the while loop (see How to interpret blocking vs non blocking assignments in Verilog?).

The non-blocking assignment schedules i to be updated after active event processing has completed. However, active event processing will never complete, because the while condition will continue to evaluate as true.

Alternatively, you could add delay within the while loop: @(posedge clk) i <= i + 1.

stuck in while loop verilog

1 Answers