verilog compile error - "variable not constant"

Question

Why am I getting error "q is not constant"?

module prv(
    input [7:0]x,
    input [7:0]y,
     output [49:0]z
     );

    wire [24:0]q;
    assign z=1;
  genvar k;

 for (k=50; k<0; k=k-1) 

   begin

     wire [25:0]a;
     assign a=0;
     assign q= x;
     genvar i;
     for(i=0; i<8; i=i+1)
      begin
        if(q[0]==1)
           begin
            assign a=a+z;
           end
        assign {a,q}={a,q}>>1;  
       end
      assign z={a[24:0],q};
    end

 endmodule

I am going to make a wild guess that this is an attempt to make a sequential multiplication like this one (Figure 3-13) users.utcluj.ro/~baruch/book_ssce/SSCE-Shift-Mult.pdf . If so, it needs a good amount of work to do it correctly. First and foremost, Verilog is a hardware descriptive language, and as such, should map very directly to the hardware it attempts to describe. The block above has none of the registers needed for the circuit provided. Please let me know if you'd like me to flesh this explanation into a full answer. — Unn

mcleod_ideafix mcleod_ideafix · Accepted Answer · 2015-10-02T11:28:03

I'm afraid that you are trying to use Verilog the wrong way. q is a wire, not a variable (a reg) so it cannot be assigned with a value that includes itself, because that would cause a combinational loop. You are using the assign statement as if it were a regular variable assignment statement and it's not.

Declare a and q as reg, not wire. i and k don't need to be genvars variables, unless you are trying to generate logic by replicating multiple times a piece of code (description). For for loops that need to behave as regular loops (simulation only) use integer variables.

Besides, behavioral code must be enclosed in a block, let it be combinational, sequential, or initial.

A revised (but I cannot make guarantees about its workings) version of your module would be something like this:

module prv(
    input wire [7:0] x,
    input wire [7:0] y,
    output reg [49:0] z
    );

    reg [24:0] q;
    reg [25:0] a;
    integer i,k;

    initial begin
       z = 1;
       for (k=50; k<0; k=k-1) begin
         a = 0;
         q = x;
         for (i=0; i<8; i=i+1) begin
           if (q[0] == 1) begin
              a = a + z;
           end
           {a,q} = {a,q}>>1;  
         end
       z = {a[24:0],q};
    end
 endmodule

verilog compile error - "variable not constant"

1 Answers