Verilog error: value is not a constant?

Question

I have a program with inputs and outputs designated as follows:

module RegBlock(
    input [31:0] WriteRegData,
    input [4:0] rs, rt, WriteRegIn,
    output [31:0] op1, rtData
    );

    reg [31:0] op1, rtData, data [0:31];

'data [0:31]' is an array that is declared afterwards, and after the declarations I've tried to assign the outputs as follows:

    assign op1 = data[rs];
    assign rtData = data[rt];
    assign data[WriteRegIn] = WriteRegData;

I keep getting an error that "WriteRegData" is not a constant. Since it's just declared as an input in the beginning of the program, I'm not sure what the problem is. I'm using Xilinx ISE.

Qiu Qiu · Accepted Answer · 2015-11-08T16:31:08

When you use continuous assignment like:

assign data[WriteRegIn] = WriteRegData;

you can't change index on the left-hand-side. You might want to use procedural assignment inside the always process to achieve what you want:

always @(*)
    data[WriteRegIn] = WriteRegData;

Verilog error: value is not a constant?

1 Answers