MMU and TLB miss

Question

Suppose the following. I have a system with virtual memory with one lever paging, I have a MMU and the TLB thing is controled by software.

Ok.. so imagine I'm a process, and I want to read a word in RAM of virtual address vaddr.

So, the CPU gives the MMU vaddr, the MMU checks in the TLB if there's an entry with the (suppose) 5 most significant bits of vaddr. If it's there... all's ok, it calculates the physical address and all goes fine.

Now.. suppose it wasn't in the TLB. In this case, the MMU makes an interrupt (a page fault). Ok.. now I'm in the handler of the page fault.

In the PBR (page base register), I have the address of the start of the page table. My question here. Is this address a physical one?. I guess yes, because if it were virtual, would means two things: 1) Must be reserved somehow in the virtual adress space of the process (never heard of something like that) 2) If this address is not in the TLB, would couse again a pagefault and I'll have an infinite loop.

Same question about addresses in tables. If I had a two level paging. The address in an entry in the first level table (that points to the second level table), is somehow virtual or physical?

Thanks.

Answer 1

Homework?

In any case, such things are in detail described in the CPU's architecture manual (and you haven't even written which CPU you're talking about - x86 does not generate page faults on TLB misses).

Answer 2

as @zvrba pointed out that behaviour is defined by CPU implementation, so this question is not answerable per se.

General things to consider though:

In the PBR (page base register), I have the address of the start of the page table. My question here. Is this address a physical one?

• yes, that has to be physical address, otherwise MMU would need to resolve virtual-to-physical address for a translation table first.
  
  

1) Must be reserved somehow in the virtual adress space of the process

• wrong, virtual should be 'translated'. So reservation doesn't make sense.
  
  

2) If this address is not in the TLB, would couse again a pagefault and I'll have an infinite loop

• good try but still wrong thinking, even if addresses holding translation tables are mapped, you still need to get physical address first to read them (TLB tables, I mean) out of memory. Otherwise you are stuck on getting virtual-to-physical for first level TLB, not ever reaching point to get your general RAM access.
  By the way, TLB tables are usually mapped into virtual address space, that's how OS mapping/unmapping memory pages for applications.
  
  

If I had a two level paging. The address in an entry in the first level table (that points to the second level table), is somehow virtual or physical?

• page walk is by physical addresses, no matter how many levels are there. See above.
  
  

I have a system with virtual memory with one lever paging... So, the CPU gives the MMU vaddr, the MMU checks in the TLB if there's an entry with the (suppose) 5 most significant bits of vaddr

• 5 most significant bits... hmm... Let's say that's 32b system so 5 most significant mean only bits [31..27] has effect. That concludes you have a page size 2^27 = 128MB. Why to bother with MMU if you could have only 32 pages mapped??? Keep MMU off!!!