Providing physical address directly to the TLB in x86-64

0
votes

Is it possible to provide physical address for a given virtual address in a direct way to the TLB on x86-64 architectures in long mode?

For example, lets say, I put zeros in PML4E, so a page fault exception will be triggered because an invalid address will be found, during the exception can the CPU tell the TLB by using some instruction that this virtual address is located at X physical page frame?

I want to do this because by code I can easily tell where the physical address would be, and this way avoid expensive page walk.

1
operating-systemx86-64tlb
How will you know what frame the address will be in? Isn't it random every time? – Trevor Arjeski
It will only be expensive if you do it in software instead of in hardware (TLB), spending many cycles to save and restore the CPU registers and manage some other kernel data structures on the way to the exception handler and back. – Alexey Frunze

1 Answers

0
votes

No, you need to put a page to the TLB. To be precise, you need to create/update appropriate PTE (with PDE and PDPE if needed). Everything around MMU management is somehow based on page tables and TLB. Even user/supervisor protection mode is done as a special flag of mapped page.

Why do you think that "page walk" is expensive operation? It is not expensive at all. To determine the PTE that must be updated you need to dereference only 4 pointers: PML4E -> PDPE -> PDE -> PTE. These entries are just indices in related tables. To get PML4E you need to use 39-47 bits of address taken during page fault handling and use the value as an index in PML4 table. To get PDPE you need 30-39 bits of an address as an index in PDE table and so on. It's not the thing that can slow down your system. I think allocation of a physical page takes more time than that.