Relation between cache and TLB hit ratios

Question

Following is the discription of the MMU of an operating system (Gate 2003 OS):

A processor uses 2-level page table for virtual to physical address translation. Page table for both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are 4 a bytes wide. Further, the processor has a translation look aside buffer (TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit ratio of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 1ns.

Question is:

How cache with 90% hit ratio and TLB with 96% hit ratio are related? Where does the OS check first: for data or instruction?

Answer 1

Cache is of prime importance and what is not cached is contained in TLB..hence the access time would be = Cache Hit + Cache Miss(TLB Hit + TLB miss).

Answer 2

Cache - Keeps the most recently used page frames. Store actual Page Frames.

TLB - Keeps mapping of the page frames that were used recently. Keeps mapping(Virtual to Physical).

From, TLB or Page table ,OS knows whether requested page frame is in the cache or not.

Answer 3

TLB HIT time= .96(Ttlb)+(.9*Tcache+.1*Tmem)

TLB MISS time =.04(Ttlb+3*(.9*Tcache+.1*Tmem))

total =TLB HIT time + TLB MISS time =3ns approx

Answer 4

First of all it's not OS who's checking for data, it is the processor. Now, the cache can be either virtually addressed or physically addressed. In the former case it comes before TLB and in the latter case it comes after TLB (TLB behaves like a cache for page table which is used to convert virtual address to physical address). Here, in the question it's clearly mentioned "physically addressed cache". So, TLB should come before cache.