VHDL Compile error

0
votes

trying to figure out why this VHDL code keeps giving back compile errors. I cannot get it to like the code no matter what I try.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity LabM5 is
  port(
     X : in STD_LOGIC;
     Y : in STD_LOGIC;
     Z : out STD_LOGIC
     );
end LabM5;

architecture behv of LabM5 is
begin
  process(X, Y)
    begin
        if (X='1' and Y='1')then Z='1'; end if; 
    end process;

end behv;

errors are:

Error: COMP96_0015: Lab M5.vhd : (16, 30): ';' expected.
Error: COMP96_0019: Lab M5.vhd : (16, 30): Keyword "end" expected.
Error: COMP96_0019: Lab M5.vhd : (16, 40): Keyword "process" expected.
Error: COMP96_0015: Lab M5.vhd : (17, 7): ';' expected.
Error: COMP96_0016: Lab M5.vhd : (17, 14): Design unit declaration       expected.

line 16 is the if statement and line 17 is the end process

2
compilationcompiler-errorsvhdl

2 Answers

2
votes

Port and signal assign is made with <= in VHDL, so change the assign in if to Z<='1'.

Btw; when will Z get any other value than '1' ?

1
votes

You'll make that mistake many times, since the equal operators are very different than other languages.

  1. Variable: Use := to assign a value.
  2. Signal: Use <= to assign a value.
  3. Starting Value: Use := to assign the starting value, even if you're defining a signal.