VHDL Error for beginner-ish

Question

It's been 2 years since my intro to VHDL course and I need to refresh myself on VHDL for a class project I have now. I am starting off with the build of a 4-bit CLA adder, and am working on a testbench. I am getting the following errors, and I don't know why. I'm pretty sure this is how it should look, but my memory might be off. Please help me.

Oh, and for reference, the errors are on the first signal declaration for a

Error: COMP96_0019: adder_tb.vhd : (45, 53): Keyword 'begin' expected.
Error: COMP96_0016: adder_tb.vhd : (45, 54): Design unit declaration expected.

My testbench code:

l

ibrary IEEE;
use IEEE.STD_LOGIC_1164.all;

entity adder_tb is   
end adder_tb;

architecture behavior of adder_tb is 
    -- Initialize the inputs/outputs of the unit to be tested
    component cl_adder_4bit
        port(
            a : in std_logic_vector(3 downto 0);
            b : in std_logic_vector(3 downto 0) ;
            c_in : in std_logic := '0';
            sum : out std_logic_vector(3 downto 0);
            c_out : out std_logic
        );
    end component;

-- Signal declarations for stimulation    
    signal a : std_logic_vector(3 downto 0) := "0000";  //initial value will be 0;
    signal b : std_logic_vector(3 downto 0) := "0000";
    signal c_in : std_logic;
    signal sum : std_logic_vector(3 downto 0);
    signal c_out : std_logic;

begin 
    uut: cl_adder_4bit port map(
        a <= a;
        b <= b;
        c_in <= c_in; 
        sum <= sum;
        c_out <= c_out;
    );              

    stimulate: process
    begin        
        --This loop is for when c_in = 0
        for i in 0 to 15 loop         
            -- This loop increments vector signal a, starting at b = 0x0
            for j in 0 to 15 loop
                wait for 5 ns;  //wait for 5 ns
                a <= a + 1;
            end loop; 
            -- This loop increments vector signal b, starting at a = 0xF
            for k in 0 to 15 loop
                wait for 5 ns; 
                b <= b + 1;
            end loop;
            a <= a + 1;
            b <= b + 1;
        end loop;
        --This second run is for when c_in is 1
        for i in 0 to 15 loop
            c_in <= '1';
            -- This loop increments vector signal a, starting at b = 0x0
            for j in 0 to 15 loop
                wait for 5 ns;  //wait for 5 ns
                a <= a + 1;
            end loop; 
            -- This loop increments vector signal b, starting at a = 0xF
            for k in 0 to 15 loop
                wait for 5 ns; 
                b <= b + 1;
            end loop;
            a <= a + 1;
            b <= b + 1;
        end loop;
    end process;

end adder_tb;

Have no access to modelsim right now, but - where is the corresponding entity? — Andy
No, I mean the entity of the testbench. There is only the architecture. You need both. Also, "end adder_tb" - this is the way how you should end the entity. The architecture you can end with "end architecture;" — Andy
Since this is a testbench, the entity would just be empty right? "entity #### is" then "end ####" right after? — dabr david
Yes, exactly. It should be named adder_tb, since your architecture already refers to it. — Andy

Unknown Unknown · Accepted Answer · 2014-11-15T19:39:08

How about

signal a : std_logic_vector(3 downto 0) := "0000";  //initial value will be 0;

Should use a VHDL comment indication:

signal a : std_logic_vector(3 downto 0) := "0000";  -- initial value will be 0;

Or your comment is a bit superfluous anyway.

Commas as separators and you associate elements in a port map:

uut: cl_adder_4bit port map(
    a <= a;
    b <= b;
    c_in <= c_in; 
    sum <= sum;
    c_out <= c_out;
);

Should be:

uut: cl_adder_4bit port map(
    a => a,
    b => b,
    c_in => c_in, 
    sum => sum,
    c_out => c_out
);

Another incorrect comment delimitation:

        wait for 5 ns;  //wait for 5 ns

Should be:

        wait for 5 ns;  -- wait for 5 ns

(The above in two places)

The the end statement for the architecture:

end adder_tb;

Should be either:

end architecture;

or

end architecture behavior;

or

end behavior;

Then because you're using the adding operator you need a use clause with an appropriate package, which in this case looks it should be Synopsys's std_logic_unsigned (in)conveniently tucked away in library ieee:

(At the top of your design file):

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

VHDL Error for beginner-ish

1 Answers