VHDL assert testbench with for loop

Question

I've a VHDL problem: for a homework we've to write a testbench with assert for our VHDL designed circuit. We should test every signal combination for a for bit comparator. I thought to solve this with a for loop, like this:

architecture ts of testbench is

signal a: std_logic_vector(3 downto 0) := "0000";
signal b: std_logic_vector(3 downto 0) := "1011";
signal c1, c0: std_logic := '0';

begin
TEST: entity forBitVergleicher port map(a, b, c1, c0);

  for i in 0 to 2**n loop
    k for k in 0 to 2**n loop

    a <= std_logic_vector(i); b <= std_logic_vector(k);
    assert(unsigned(a) > unsigned(b) and (c1 = '0' or c0 =
    '1') and (c1 = '0' and c0 = '0') and (c1 = '1' and c0 =
    '0')) 
    report "error";

    assert(unsigned(b) > unsigned(a) and (c1 = '1' and c0 =
    '0' or c1 = '0' and c0 = '0' or c1 = '1' and c0 = '0'))
    report "error";

    assert(a = b and ((c1 = '1' and c0 = '1') or (c1 /= c0)))
    report "error";

First of all I tested the idea (for loop etc.) in Python, to check if it works (it did). Well, now I've no idea why my VHDL code doesn't work. I've got many error reports which doesn't make sense in my mind. Have anyone an idea?

COMP96 ERROR COMP96_0329: "Generate statement must have a label." "testbench.vhd" 18 3 COMP96 ERROR COMP96_0019: "Keyword 'generate' expected." "testbench.vhd" 18 22 COMP96 ERROR COMP96_0661: "Expression with a sequence of different logical operators is not allowed. Parenthesize subexpressions containing and, or, xor, and xnor operators." "testbench.vhd" 28 9 COMP96 ERROR COMP96_0016: "Design unit declaration expected." "testbench.vhd" 35 4

If you need I've a link for the whole VHDL Code: https://www.edaplayground.com/x/4c2n

Couple of suggestions: Put the loops inside a process, add wait after having applied the stimuli on a and b and before testing the output on c0 and c1. — Morten Zilmer

Harry Harry · Accepted Answer · 2019-12-25T09:59:13

You can't use a for ... loop outside a process (or function/procedure). You should either put the for ... loop inside a process (or function/procedure), or use a for ... generate loop.

However, if you use a for ... generate loop (outside a process), then note that it must have a label (as described by one of your error messages). For example:

loop_label : for i in 0 to 2**n generate
...
end generate;

In your specific case, I would recommend using a for ... loop inside a process (with a wait statement at the end).

There are quite a lot of other problems with your code, but this will at least help you to get past this first error.

Some other issues to look at:

n has not been defined.
k for k in ... should be for k in ...
0 to 2**n will loop 2**n + 1 times. You probably want 0 to 2**n-1.
std_logic_vector(i) and std_logic_vector(k) are illegal. You probably want std_logic_vector(to_unsigned(i, 4)) etc.
Your assert statements should probably have a severity specified. For example, assert <something> report "error" severity failure;
Your indentation is incorrect, which makes it much more likely that you will make mistakes. Your loops should be indented more like this:

for i in 0 to 2**n-1 loop for k in 0 to 2**n-1 loop a <= std_logic_vector(to_unsigned(i, 4)); b <= std_logic_vector(to_unsigned(k, 4)); ... end loop; end loop;
Your logical expressions like <a> and <b> or <c> are meaningless and will be rejected by the compiler. Do you mean (<a> and <b>) or <c> or <a> and (<b> or <c>). It is important to understand which you want and parenthesize appropriately.
It is usually considered bad practice to mix languages in your code. Choose either German or English and stick to it.

VHDL assert testbench with for loop

1 Answers