')' expected. - VHDL

Question

A piece of my VHDL code is:

                133 if(grupo = '000' or grupo = '111') then -- 0
                                
                134 elsif(grupo = '001' or grupo = '010') then -- 1
                                    
                135 elsif(grupo = '011') then -- 2
                                    
                136 elsif(grupo = '100') then -- -2
                                    
                137 elsif(grupo = '101' or grupo = '110') then  -- -1
                    
                138 end if;

However, this errors came:

Error: COMP96_0049: Multiplicador.vhd : (133, 17): Syntax error in expression.

Error: COMP96_0015: Multiplicador.vhd : (133, 17): ')' expected.

Error: COMP96_0019: Multiplicador.vhd : (133, 18): Keyword 'then' expected.

Error: COMP96_0019: Multiplicador.vhd : (141, 6): Keyword 'end' expected.

Error: COMP96_0049: Multiplicador.vhd : (141, 20): Syntax error in expression.

Error: COMP96_0015: Multiplicador.vhd : (141, 20): ')' expected.

Error: COMP96_0019: Multiplicador.vhd : (141, 21): Keyword 'then' expected.

Error: COMP96_0019: Multiplicador.vhd : (147, 9): Keyword 'process' expected.

Error: COMP96_0015: Multiplicador.vhd : (150, 8): ';' expected.

Error: COMP96_0016: Multiplicador.vhd : (150, 10): Design unit declaration expected.

But I can't find a solution. The error is in this part.

You should probably double-check the number of open parentheses you have with respect to close parentheses. — Makoto

Unknown Unknown · Accepted Answer · 2014-09-21T08:03:23

There's probably more than one thing wrong in your code. Just showing lines with reported syntax errors isn't always adequate. Sometimes the actual error can be in a preceding line.

 if(grupo = '000' or grupo = '111') then

The lexical element ' (apostrophe) is only acceptable to either indicate an attribute, indicating the target of a qualified expression or as part of a character literal.

'000' etc. are none of these. An attribute name is an identifier, as is a type name used to specify the type an aggregate should be treated as.

Should these be using parentheses? ("000", "111", etc.)

You haven't provided enough sample code to reproduce the errors.

This successfully analyzes:

entity multiplicador is
end entity;

library ieee;
use ieee.std_logic_1164.all;

architecture que of multiplicador is
    signal grupo:   std_logic_vector(2 downto 0);
begin
UNLABLED:
    process (grupo)
    begin
        if (grupo = "000" or grupo = "111") then -- 0

        elsif(grupo = "001" or grupo = "010") then -- 1

        elsif(grupo = "011") then -- 2

        elsif(grupo = "100") then -- -2

        elsif(grupo = "101" or grupo = "110") then  -- -1

        end if;
    end process;
end architecture;

')' expected. - VHDL

1 Answers