if statement not working as expected in vhdl

Question

Below is the a part of a code describing a FSM.

clk_process : process
  begin
wait until clk'event ;
if(clk ='0') then
  if( state = s2) then
  state <= nextstate;
  end if;
elsif clk='1' then
  state <= nextstate;
end if;  
end process clk_process;

state <= nextstate statement is not being executed even when clk='0' , state=s2 and clk event has occurred. Can anyone reason why this weird behavior is should. What can I do no to do what i intent to do.

Thanx

Edit 1:

library ieee;
use ieee.std_logic_1164.all;

entity machine is
  port(clk : in std_logic; out1,out2 : out std_logic);
  end entity;

architecture behave of machine is
  type statetype is (s0,s1,s2,s3,s4);
  signal state,nextstate : statetype :=s0;
  begin    
--    nextstate<=s0;
  comb_process: process(state)
  begin
    case state is
    when s0 =>
      nextstate <= s1;
    when s1 =>
      nextstate <=s2;
      out1 <= '1';
      out2 <= '1';
    when s2 =>
      if(clk ='0') then
        nextstate <= s3;
        out2 <='1';
      else
        nextstate <=s2;
        out1<='0';
        out2<='0';
      end if;
    when s3 =>
      nextstate <= s4;
    when s4=>
      nextstate <= s1;
    end case;
  end process comb_process;
  clk_process : process
  begin
    wait until clk'event ;
    if(clk ='0') then
      if( state = s2) then
      state <= nextstate;
      end if;
    elsif clk='1' then
      state <= nextstate;
    end if;
  end process clk_process;
end behave;

This is my full code. What i am trying to do is when state is S2 it should be both positive and negative edge triggered

Show more design specification including declarations. Any assignments to state outside clk_process? What's the value of state and nextstate? Your process by itself doesn't sufficiently demonstrate the problem which you ascribe to it. See How to create a Minimal, Complete, and Verifiable example, noting that your provided process statement uses separators and parentheses inconsistently no parentheses shown are needed, the elsif clk='1' could simply be else and it isn't likely that using both clock edges is universally eligible for synthesis. — user1155120
I am trying to model circuit for the problem 8.2 in page 195 of link — Aditya
What you're trying to do doesn't provide any more useful information. This is an issue with what your VHDL code does and you haven't shown enough. — user1155120
Just an FYI. That book's suggestion to design an FSM with outputs clocked on both edges is a bad idea. In the rare cases where you have to double clock logic (without dedicated DDR I/O) it needs to be isolated to the smallest bit of logic possible. You can't control that if it's mixed in with FSM next-state generation and output decode. — Kevin Thibedeau
Do you plan on implementing what you have in a chip? Does the chip have DDR registers? Do they have a recommended method for coding dual edge/DDR flipflops? If they do not have DDR flops, this impacts your desired hardware and how you write your code. Draw a picture of your desired hardware that uses the resources the chip does have, and then write the code. BTW, your current code will not simulate correctly because you need CLK on the sensitivity list of comb_process. Good luck. — Jim Lewis

pwolfsberger pwolfsberger · Accepted Answer · 2014-11-05T00:14:10

The problem with your code seems to be that your state machine will get stuck when state = s1 and nextstate = s2. When it gets to this point, the next rising clock edge will cause the clk_process block to change state <= s2. This will cause your comb_process block to trigger while clk = '1', thus causing nextstate <= s2. Once state is equal to nextstate, comb_process will never trigger again.

If you don't care about the number of states bits used for you FSM, you could simply create a state for each clock transition event.

if statement not working as expected in vhdl

Thanx

1 Answers