Reset in Mealy finite state machine

Question

I have some issues with the reset signal in a Mealy finite state machine in VHDL. I have created a very simple Mealy FSM for easier understanding. The FSM has two process, one synchronous for the calculation of the state, and one combinational for the calculation of the outputs and the next state. The issue I have is that when reset = '1' and input1= "11" then output1="11" when it should be output1 ="00"

This can be solved by: including the reset input in the sensitivity list of the combinational block. Or by evaluating the reset signal at state s0 ( for example if input1="11" and rst = '0'then ). Nevertheless I didn't see these "solutions" in any literature, so there is where my doubts are. Below is the source code.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;

entity fsmtest is
  
  port (
    clk  : in  std_logic;
    rst : in std_logic;
    input1  : in std_logic_vector(1 downto 0);
    output1  : out std_logic_vector(1 downto 0));


end fsmtest;

architecture rtl of fsmtest is

  type state is (s0, s1);
  signal st, next_state : state := s0;


begin  -- rtl

  process (clk, rst)
  begin --process
    if rst = '1' then
      st <= s0;
      --next_state <= s0;
    elsif clk'event and clk = '1' then  -- rising clock edge
      st <= next_state;
    end if;
  end process;

  process(st, input1)
    begin  -- process

      case (st) is
        when (s0) => --initial state
          if input1 = "11" then
          next_state <= s1;
          output1 <= "11";
          else
          next_state <= s0;
          output1 <= "00";
        end if;

        when (s1) => --wait10
          if input1 = "00" then
            next_state <= s0;
            output1 <= "00";
            else
              output1 <= input1;
              next_state <= s1;
          end if;     
      end case;
  end process;
end rtl;

It is easier and less error prone to write a single-process state machine. — scary_jeff
I disagree with the above statement. There are advantages to writing a single-process FSM, but I would say it is certainly less error prone to use two processes as above, one purely sequential and combinational. This is because outputs from a single-process FSM are registered (which is an advantage), but because of that, each output has to be anticipated one clock cycle in advance. This requires some kind of mental transformation between the state diagram and the HDL code, which is where errors can creep in. — Matthew Taylor
Another useful feature is that you can write code like if next_state==B then... In a single process FSM you have to track down all cases where you go to state B. (And hope you don't forget the 'then' section if you make a change) In a split process you can just use the code above. — Oldfart

Matthew Taylor Matthew Taylor · Accepted Answer · 2018-05-08T09:11:37

When rst = '1' and input1= "11" then output1="11". That's what you have written in your code. You have written:

  process (clk, rst)
  begin --process
    if rst = '1' then
      st <= s0;

so st is s0 when rst is '1' and then you have written

  process(st, input1)
    begin  -- process
      case (st) is
        when (s0) => --initial state
          if input1 = "11" then
            output1 <= "11";

so output1 is "11" when st is s0 and input1 is "11".

Reset in Mealy finite state machine

1 Answers