VHDL process does not synthesize as expected

Question

I have a bit of trivial looking VHDL code which is driving me crazy. I have an external logic bit connected to a signal called 'inint'. The signal is then used in a process that looks as follows:

process(inint)
  begin
    if rising_edge(inint) then
      extint <= '1';
    end if;

    if falling_edge(inint) then
      extint <= '0';
    end if;

  end process;

When I synthesize tis code though, only the lower part of the code is synthesized and not the upper part. What am I missing here?

I am guessing it is something very elementary but cannot put a finger on it. Any help would be greatly appreciated.

Regards,

Shailesh

What makes you think it's not being synthesized? Have you simulated it? — Valueduser
The tool may have a problem mapping the VHDL to available hardware; see this. Check the synthesis warnings; if the synthesis result is not equivalent with the VHDL code, then there should be a warning telling about the problem. The code simply describes extint <= inint, so I wonder if that is really the intention. If you really want to update on both rising and falling edge of an external signal, then you may have to use a DDR input buffer. — Morten Zilmer
the synthesis messages say that the elements are being removed as they are unused. What i am trying to do here is to simply set a flag here when a positive edge is detected. I would ideally use another signal to reset the flag so imagine the process with another signal entry and an if statement for the second signal as well. The code won't work still. Where is the flaw in my approach? — BombayBlue
For update of a flag at rising_edge(inint), and clear at e.g. a reset, the you simply want a flip-flop with asynchronous reset, as described in this, also in previous comment. — Morten Zilmer
"Only one clock edge per process" is a pretty good basic rule for synthesisable code, at least with the technologies we have now. — user_1818839

Ian Ian · Accepted Answer · 2015-11-02T13:52:48

The correct way to do this is with a double data rate register. Otherwise you can't synthesize logic that toggles at the clock rate. The Xilinx primitive you need is called an ODDR and is documented in the Select IO Resources User guide for your device (here is the one for the Artix-7, see page 127).

It can be instantiated to do what you're trying to do like this:

ODDR_INST1 : ODDR
generic map (
    DDR_CLK_EDGE => "SAME_EDGE",
    INIT         => '0',
    SRTYPE       => "SYNC"
) 
port map (
    Q  => extint,
    C  => inint,
    CE => '1',
    D1 => '1',
    D2 => '0',
    R  => '0',
    S  => '0'
);

As an added note trying to imply a double data rate output (which is what your code does) is not a good idea. Its probably not supported, but also as a general rule if you need special purpose hardware (which you do), you should instantiate it directly because its hard to guarantee when the tools will infer (though they are much more deterministic than they used to be).

VHDL process does not synthesize as expected

1 Answers