I don't understand what's wrong with this VHDL code?

Question

I have the following code:

entity wave_select is
port( address:in std_logic_vector(6 downto 0);
ws1: in std_logic;
ws0: in std_logic;
wave_out: out std_logic_vector(6 downto 0));
end wave_select;


architecture choose_arch of wave_select is
signal internal_sine:std_logic_vector(6 downto 0);
signal internal_tri:std_logic_vector(6 downto 0);
signal internal_sqr:std_logic_vector(6 downto 0); 

begin 
U0: entity sine_tbl port map(addr=>address, sine_val=>internal_sine);
U1: entity triangle_tbl port map(addr=>address, tri_val=>internal_tri);
U2: entity square_tbl port map(addr=>address, square_val=>internal_sqr);

    process (std_logic_vector'(ws1, ws0))
    begin
        case ws_combo is
            when "01" => wave_out<=internal_sine;
            when "10" => wave_out<=internal_tri;
            when "11" => wave_out<=internal_sqr;
            when others =>wave_out<=(others => '-');
        end case;
    end process;


end choose_arch;`

Whenever I try to compile this, I get the following errors:

Identifier/keyword expected (for the process line)
Keyword end expected (for the when "10" line)
Design unit declaration expected (for the same line as keyword error)

FIXED THE QUESTION

Jerry Coffin Jerry Coffin · Accepted Answer · 2013-04-25T00:04:16

As it stands right now, this has a number of problems, mostly with fairly basic syntax.

Although it seems likely you mean the combination of ws0 and ws1 to be treated as ws_combo, you haven't done anything to tell the synthesizer that, so it treats ws_combo as simply undefined.

At least as far as I know, you can't combine signals in the process sensitivity list like you've done. The sensitivity list is to tell what external signals this process responds to, not much else.

You don't have a definition of wave_out (unless it's also in your entity declaration).

You don't have definitions of internal_sine, internal_tri, or internal_sqr. Hard to guess what type they should be without knowing the type of wave_out.

As an interim idea of how this might turn out, I've fixed some of the syntax errors, added an entity declaration that declares ws0, ws1 and wave_out, then sets wave_out to values suitable to the type I've given it (in this case, just took binary input and produced Grey code output).

entity controller1 is
port (
    ws1 : in std_logic;
    ws0 : in std_logic;
    wave_out : out std_logic_vector(1 downto 0)
);
end;

architecture whatever of controller1 is
begin
impl: process(ws0, ws1)
    begin
        case std_logic_vector'(ws1,ws0) is
            when "01" => wave_out<="01";
            when "10" => wave_out<="11";
            when "11" => wave_out<="10";
            when others =>wave_out<=(others => '-');
        end case;
    end process;
end whatever;

Of course, this also needs the typical library and using to get declarations for std_logic and std_logic_vector, but with those added the synthesizer seems to accept it. Of course, some other synthesizer (I'm checked it with Synplify) might find a problem I missed, but I think that probably covers at least most of the obvious problems.

I don't understand what's wrong with this VHDL code?

2 Answers