VHDL: Concat inout std_logic into std_logic_vector signal

Question

I have several tri-stateable (inout) std_logic port pins defined in my top-level port declaration. I have a dedicated internal component that is needing to utilize these, but its port is defined as having an inout std_logic_vector (not my code and I can't change), which I need to concatenate my std_logic into a std_logic_vector to make it happy.

The problem is: I'm not sure how to do this.

I thought that ALIAS would be the correct route, but apparently the concatenation operator can't be used when defining an alias.

Then I thought I'd just use a std_logic_vector internal signal:

mySignal <= inOutBit2 & inOutBit1 & inOutBit0; --Input route

componentPort => mySignal, --Component use

inOutBit2 <= mySignal(2);
inOutBit1 <= mySignal(1);
inOutBit0 <= mySignal(0); --Output route

but this would not synthesize as it viewed inOutBitn as having multiple drivers.

Is there anything I can do to get this to synthesize? I know I can just declare my top-level inout port to be a std_logic_vector, but that is sub-optimal as we have a a well defined port-labeling convention.

Can't you use mySignal(0) <= inOutBit0 etc. instead of the first line? — sinelaw
For a standard VHDL signal, there is no difference between assigning each bit of a vector or using concatenation to assign the entire vector in 1 line. Or are you saying that there is a difference when it comes to inout ports? — jerp
My mistake; you're right. Can you add some more code (the definitions) and the synthesis error / wrong result? — sinelaw

Morten Zilmer Morten Zilmer · Accepted Answer · 2014-02-27T17:51:55

Based on your description, I understand that both the top-level ports and the component ports are mode inout.

If this is so, then it may help if you connect the component ports directly to the external inout ports at std_logic level, like:

componentPort(0) => inOutBit0,  --Component use
componentPort(1) => inOutBit1,  --Component use
componentPort(2) => inOutBit2,  --Component use

The intermediate mySignal is then not required.

However, the description says that synthesis reports multiple drivers for inOutBitn, but I would expect that it reported multiple drivers for mySignal in the original code.

VHDL: Concat inout std_logic into std_logic_vector signal

1 Answers