Register variable in port declaration in verilog

Question

I want to make a module in Verilog which must get a 32 bit wide register variable in port. This variable will be used to count the clock cycle. Then this module will be instantiated in another module. For example: when I fix the value of counter this module must start count from that value.

When I simulate this code I get an error:

Non-net port count cannot be of mode input

module case_1( input clk , input [31:0] counter);
  reg [31:0] counter;

  always @ (posedge clk)
    begin
      counter <=counter +1
    end

endmodule

module counter (input clk , input [31:0] counter )
  reg [31:0] counter;
  case_1 h1  ( .clk(clk) , .counter(counter) )
endmodule

You defined counter as an input signal and a register at the same moment. This is not possible. — Qiu
in case_1 you have counter as an input, then drive a value onto it. If your driving the value should it not be an output? — Morgan

Morgan Morgan · Accepted Answer · 2014-12-26T17:03:22

If a module is an input then you can not drive a value on to it. Driving a value on to an input does not make sense. It needs to be an output.

It think there might be some confusion over the reg and wire types in verilog. These types do not cross module interfaces. a lower (sub) module drives its output as a reg type. the next level up a wire is connected to the port.

From your example a clock received by counter which uses sub module case_1 to implement the counter. Counter value is then driven (first as a reg) then at the top level as a wire.

module case_1( 
  input clk ,
  output reg [31:0] counter
);

  initial begin
    counter = 'b0;
  end

  always @ (posedge clk) begin
    counter <=counter +1;
  end

endmodule

module counter (input clk , output wire [31:0] counter );
  case_1 h1  ( .clk(clk) , . counter(counter) );
endmodule

Example on EDA Playground.

Register variable in port declaration in verilog

1 Answers