Shift Register in verilog

Question

I have designed a serial in parallel out shift register as input register for an encoder

module ShiftRegister_SIPO(clk, in, out);
input clk,in;
output [3:0] out;
reg [3:0] tmp;

always @(posedge clk)
begin
tmp = {tmp[2:0], in};
end
assign PO = tmp;
endmodule

how do I retain the value once the desired parallel out data is got , even with clk=1? Because even after the output data is got the value keeps shifting. For example ,if i give
Part of testbench

in=1;
#10
in=0;
#10
in=1;
#10
in=1;

#5 clk=~clk;

I get 1011 at the 4th clock cycle , but the value then keeps shifting. Can i retain it as 1011 for the remaining period also, still keeping the clk=1. Thanks in advance

Serge Serge · Accepted Answer · 2021-03-30T02:18:13

In you example the value will be shifting every positive edge of the clock. In order to prevent it from shifting under some circumstances you need a way to enable or disable shifting. For example:

always @(posedge clk)
begin
   if (enable)
      tmp <= {tmp[2:0], in};
end

So, controlling the enable signal you can control shifting. If its value is low, then no shifting will happen and the value of 'tmp' will remain unchanged till you enable it again.

Shift Register in verilog

1 Answers