ERROR:Simulator:702 - Can not find design unit work.glbl ... when attempting Post-Route in ISim

Question

I am trying to run my project in Post-Route simulation. The behavioral simulation works fine and I want it to work on the Spartan 3E Starter board. It also is able to Generate a Programming File under implementation.

Using ISE 14.7

The error I get is:

Process "Generate Post-Place & Route Simulation Model" completed successfully

Started : "Simulate Post-Place & Route HDL Model".

Determining files marked for global include in the design...
Running fuse...
Command Line: fuse -intstyle ise -incremental -lib simprims_ver -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -o /home/alex/projects/ece369/datapath/PostRoute_tb_isim_par.exe -prj /home/alex/projects/ece369/datapath/PostRoute_tb_par.prj work.PostRoute_tb work.glbl {}
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib simprims_ver -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -o /home/alex/projects/ece369/datapath/PostRoute_tb_isim_par.exe -prj /home/alex/projects/ece369/datapath/PostRoute_tb_par.prj work.PostRoute_tb work.glbl 
ISim P.20131013 (signature 0xfbc00daa)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8 
Determining compilation order of HDL files
Analyzing Verilog file "/home/alex/projects/ece369/datapath/src/PostRoute_tb.v" into library work
ERROR:Simulator:702 - Can not find design unit work.glbl in library work located at isim/work

In the "design tab" it shows ClockDivider and DATAPATH_TEST as '?'. When I set association from 'all' to 'simulation' the files appear but I get an error about "Top module has not been specified"

From google search, I tried "cleanup project files" and also recreating the project. I also tried getting glbl.v from the /opt/Xilinx/14.7/ISE_DS/ISE/verilog/src/ and I put that in, but I am not sure what to do with it.

My testbench:

`timescale 1ns / 1ps

module PostRoute_tb();
    reg              Clk, Rst, Rst_t;
    wire             Clk_slow;
    wire    [31:0]   out_0, out_1;
    reg     [31:0]   ii;

   TopClkDiv #(25) ClockDivider(
       .Clk(Clk),
       .Rst(Rst_t),
       .ClkOut(Clk_slow)    
   );

    Datapath DATAPATH_TEST(
        .Clk(Clk_slow), 
        .Rst(Rst),
        .Rst_t(Rst_t),
        .out_0(out_0),
        .out_1(out_1)
    );

    always begin
        Clk <= 0;
        #250;
        Clk <= 1;
        #250;
    end
    initial begin
        Rst <= 1;
        Rst_t <= 1;
        ii <= 0;
        #222;
        Rst <= 0;
        Rst_t <= 0;

        while (ii < 50000) begin
            @(posedge Clk_slow)
            ii = ii + 1;
        end
    end

endmodule

This is for a class. My TA suggested: 1) Which file is set as top module when you are doing the pnr and synthesis? it should be datapath.v for given testbench. 2) Also i would remove clock_divider RTL from the testbench and generate clock using normal wait statements in the testbench. so try driving datapath clk using following clock and remove clock divider form the testbench. Add required delay. — exrhizo

beto_peto beto_peto · Accepted Answer · 2015-02-20T09:14:39

I had same error

"ERROR:Simulator:702 - Can not find design unit work.glbl ...".

In my case I moved an old ISE 14.1 project to PlanAhead 14.7. My problem and solution was to remove verilog_define={GLBL} in Project Settings -> Simulation -> "Verilog options:". Check box "Load glbl" is checked. The reason is that some simulation verilog code is encapsulated in "ifndef GLBL". You can find it by executing "find . -type f -name "*.v" | xargs grep 'def GLBL' -sl" in your PlanAhead install dir.

ERROR:Simulator:702 - Can not find design unit work.glbl ... when attempting Post-Route in ISim

1 Answers