Error: (vsim-3033) Ripple_counter.v(22): Instantiation of 'JK_flip_flop' failed. The design unit was not found

Question

When I want to compile it is okay, but when I do simulate, there are these errors:

Error: (vsim-3033) C:/DS_2020/LAB06_/Ripple_counter.v(18): Instantiation of 'JK_flip_flop' failed. The design unit was not found.

Error: (vsim-3033) C:/DS_2020/LAB06_/Ripple_counter.v(19): Instantiation of 'JK_flip_flop' failed. The design unit was not found

Error: (vsim-3033) C:/DS_2020/LAB06_/Ripple_counter.v(20): Instantiation of 'JK_flip_flop' failed. The design unit was not found.

Error: (vsim-3033) C:/DS_2020/LAB06_/Ripple_counter.v(22): Instantiation of 'JK_flip_flop' failed. The design unit was not found.

When I use other module, it's okay, but like this use sequential circuit model, there is error like this.

If you know how to remove this error, please tell me.

module JK_filp_flop(clk, J, K, Q);

input clk;
input J,K;
output Q;

reg Q;

always @(negedge clk) begin

    Q <= 1'b0;

    if(J==0 && K==0) begin Q <= Q; end
    else if(J==0 && K==1) begin Q <= 1'b0; end
      else if(J==1 && K==0) begin Q <= 1'b1; end
        else if(J==1 && K==1) begin Q <= ~Q; end
    end

endmodule



module Ripple_counter(clk, logic_1, out );
  
  input clk;
  input logic_1;
  
  output out;
  
  wire w1;
  
  wire Q8,Q4,Q2,Q1;
  
  JK_flip_flop JK1 (clk,logic_1,logic_1,Q1);
  JK_flip_flop JK2 (Q1,~Q8,logic_1,Q2);
  JK_flip_flop JK3 (Q2,logic_1,logic_1,Q4);
   assign w1 = Q2&Q4;
  JK_flip_flop JK4 (Q1,w1,logic_1,Q8);
  
  assign out = {Q8, Q4, Q2, Q1};
  
endmodule

This is testbench code:

`timescale 10ns/1ps

module Ripple_counter_TB;

reg clk;
reg logic_1;

wire w1;
wire Q8, Q4, Q2, Q1;

//clock
parameter FREQ = 50; //MHz
parameter CKP = 1000.0/FREQ;

Ripple_counter U1(clk, logic_1, Q8,Q4,Q2,Q1 );

initial forever #(CKP/2) clk = ~clk;

initial begin
clk = 1'b0;
logic_1 = 1'b1;
end
endmodule

toolic toolic · Accepted Answer · 2020-10-17T11:29:21

There are a few errors.

You have a typo in the JK name (filp). Change:

module JK_filp_flop(clk, J, K, Q);

to:

module JK_flip_flop(clk, J, K, Q);

You need to specify a bit width for out because the default is 1 bit. Change:

  output out;

to:

  output [3:0] out;

You have a connection error. You need to connect 4 bits to a 4-bit port. You can use concatenation ({}). Change:

Ripple_counter U1(clk, logic_1, Q8,Q4,Q2,Q1 );

to:

Ripple_counter U1(clk, logic_1, {Q8,Q4,Q2,Q1} );

This compiles without errors for me.

Error: (vsim-3033) Ripple_counter.v(22): Instantiation of 'JK_flip_flop' failed. The design unit was not found

1 Answers