"Invalid Module Instantiation" Error in Mealy sequence detector - Verilog

0
votes

I have defined a module for a Mealy State Machine that detects a particular sequence. I haven't encoded states as is usually a better choice as I wanted to do it the other way(I saw a similar example in a book, but the code was in VHDL).

module seq_detector(y_out,Clk,x_in);
  output y_out;
  reg y_out;
  input x_in, Clk;
  reg Q1,Q2,Q3,Q4;
  always @(posedge Clk)
    Q1 <= (Q1&&(!Q3))||((!Q1)&&Q2;&&(!Q3)&&(!Q4)&&(x_in));
    Q2 <= ((!Q3)&&Q4;&&(!x_in))||(Q1&&Q2;&&(!Q3)&&(!Q4)&&x_in);
    Q3 <= Q1&&Q2;&&(!Q3)&&(x_in);
    Q4 <= (Q1&&Q2;&&(x_in))||(Q1&&(!Q4)&&(!x_in))||((!Q1)&&(!Q2)&&(Q4)&&(!x_in))||((!Q1)&&(!Q2)&&(x_in))||((!Q1)&&(!Q3)&&Q4;&&x_in)||(Q1&&Q2;&&(!Q4)&&x_in);

  always @(x_in or Q1 or Q2 or Q3 or Q4)
  y_out <= Q3||(Q2&&(!Q4)&&x_in);
endmodule

On compiling the code, I get the following errors. 

mini_project.v:8: syntax error
mini_project.v:8: error: Invalid module instantiation
mini_project.v:9: error: Invalid module instantiation
mini_project.v:10: error: Invalid module instantiation

I can't make out anything of the error message. Can someone please explain the error message and suggest how to correct it ?

3
verilog

3 Answers

3
votes

You are missing begin and end keywords in your always block. The code thinks that you are trying to instantiate a module rather than do signal assignments. Only the first line will be captured under the always block (the Q1 assignment). The others will not. Try this:

always @(posedge Clk)
begin
  Q1 <= (Q1&&(!Q3))||((!Q1)&&Q2;&&(!Q3)&&(!Q4)&&(x_in));
  Q2 <= ((!Q3)&&Q4;&&(!x_in))||(Q1&&Q2;&&(!Q3)&&(!Q4)&&x_in);
  Q3 <= Q1&&Q2;&&(!Q3)&&(x_in);
  Q4 <= (Q1&&Q2;&&(x_in))||(Q1&&(!Q4)&&(!x_in))||((!Q1)&&(!Q2)&&(Q4)&&(!x_in))||((!Q1)&&(!Q2)&&(x_in))||((!Q1)&&(!Q3)&&Q4;&&x_in)||(Q1&&Q2;&&(!Q4)&&x_in);
end

As a side note, this code is really really really ugly. Is there a better way to do this??

1
votes

You have multiple syntax errors.

You need a begin/end in your always block.

  always @(posedge Clk) begin
    Q1 <= (Q1&&(!Q3))||((!Q1)&&Q2;&&(!Q3)&&(!Q4)&&(x_in));
    Q2 <= ((!Q3)&&Q4;&&(!x_in))||(Q1&&Q2;&&(!Q3)&&(!Q4)&&x_in);
    Q3 <= Q1&&Q2;&&(!Q3)&&(x_in);
    Q4 <= (Q1&&Q2;&&(x_in))||(Q1&&(!Q4)&&(!x_in))||((!Q1)&&(!Q2)&&(Q4)&&(!x_in))||((!Q1)&&(!Q2)&&(x_in))||((!Q1)&&(!Q3)&&Q4;&&x_in)||(Q1&&Q2;&&(!Q4)&&x_in);
  end

Even after fixing that, you have stray semicolons all throughout your code:

Q1 <= (Q1&&(!Q3))||((!Q1)&&Q2;&&(!Q3)&&(!Q4)&&(x_in));
// ---------------------------
1
votes

Coincidentally this is a current assignment in my CPE166 advanced logic design class. The main idea in the assignment is to synthesize registers correctly. Something like this (though our assignment was much more complicated with multiple possible inputs, longer sequences, reset, programmable sequences, and buttons which needed to be debounced):

module sequence_detector(
input wire x_in,clk,
output wire y_out 
);

reg [3:0] seq, seq_nxt;

parameter correct_sequence = 4'b1001;

always @(posedge clk) 
    seq <= seq_nxt;

always @(*)
    seq_nxt = {seq[2:0] , x_in};

assign y_out = (seq == correct_sequence);
endmodule

This will create a 4-bit shift register which will shift on every positive clock edge. The newest value of x_in will go in on one side and the oldest value of x_in will be shifted out. The current values of the shift register are constantly compared to the parameter correct_sequence, which when true will make y_out go high.

Synthesized Logic