connecting VHDL port to system verilog interface definition in UVM

Question

I am having this issues in the Cadence tool chain simulation when I try to connect the multidimensional user defined type in VHDL to SystemVerilog in a UVM environment. This is the VHDL output type definition:

TYPE loop_reg_ty IS RECORD
      loop_index_value    : std_logic_vector(REG_BITWIDTH-1 DOWNTO 0);
      loop_counter : std_logic_vector(REG_BITWIDTH-1 DOWNTO 0);
      loop_end_flag : std_logic;
END RECORD;

TYPE loop_array_ty is array (MAX_NO_OF_LOOPS-1 downto 0) of loop_reg_ty;

One of the VHDL output ports in my DUT is of type loop_array_ty;

I am trying to define the SystemVerilog equivalent as:

typedef struct packed {
                            bit [REG_BITWIDTH-1:0] loop_index_value;
                            bit [REG_BITWIDTH-1:0] loop_counter;
                            bit loop_end_flag;
                          } raccu_loop_reg_ty;

typedef raccu_loop_reg_ty [MAX_NO_OF_RACCU_LOOPS-1:0] loop_array_ty;

When I use irun, I get the error:

VHDL port type is not compatible with Verilog.

Please suggest the possible work around solution.

Alternatively, OSVVM allows more advanced verification in straight VHDL, avoiding the need to translate types, possibly losing type information. www.osvvm.org — user_1818839
Your loop_array_ty definitions look odd as they do not match. Shouldn't the VHDL be TYPE loop_array_ty is array (MAX_NO_OF_LOOPS-1 downto 0) of loop_reg_ty; and the SystemVerilog be typedef loop_reg_ty loop_array_ty [MAX_NO_OF_RACCU_LOOPS-1:0];? — Greg
@Greg : Yes you are correct in VHDL part..That was a typo error..In System verilog "loop_array_ty" is an array of loop_reg_ty elements. Is that a wrong representation ? — user2293385
@Greg : I am not sure how such instances are resolved. Please suggest any other possible best practices or solutions. I am not allowed to modify the DUT. — user2293385
@SunilKR, I'm experienced with SystemVerilog, not VHDL. I highly suggest reading § 7.2 Structures and § 7.4 Packed and unpacked arrays of IEEE Std 1800-2012. Then map that to VHDL arrays & records. I think a RECORD is a equivalent to a regular struct(not struct packed) and a is array is an unpacked SV array; but I don't understand VHDL enough to say for certain. — Greg

Tudor Timi Tudor Timi · Accepted Answer · 2014-12-05T19:33:57

First, your problem is that you're not defining the loop_array_ty correctly. It should be typedef raccu_loop_reg_ty loop_array_ty[MAX_NO_OF_RACCU_LOOPS-1:0].

I would suggest 2 things here:

First, try removing the packed qualifier from the struct definition. Connecting SV structs to VHDL records is something that is only available in newer Incisive versions. Make sure that the version you're using supports this.

If you're using an older version of Incisive (like I was a year back), your only choice is to map the individual record members using $nc_mirror (not tested code, but enough to get you started):

// struct definition...
// ...

module top;
  // intermediate signal we'll mirror onto
  loop_array_ty loop_s;

  // no output connected
  my_dut dut_inst();

  // make the connection between SV and VHDL using nc_mirror
  initial begin
    for (int i = 0; i < MAX_NO_OF_RACCU_LOOPS; i++) begin
      $nc_mirror($sformatf("loop_s[%0d].loop_index_value", i),
        $sformatf("dut_inst.loop_o[%0d].loop_index_value", i);

      // $nc_mirror for loop_counter
      // $nc_mirror for loop_end_flag
    end
  end
endmodule

Also make sure that you're setting the REG_BITWIDTH constant appropriately in both languages, otherwise you'll also get a type mismatch.

connecting VHDL port to system verilog interface definition in UVM

1 Answers