VHDL unconstrained records in system verilog testbenches

Question

The design to be tested is written in VHDL and uses unconstrained records like this for its ports:

type forward_stream is record
    data     : std_ulogic_vector;
    -- further members
    ...
end record;

These ports should now be driven from a systemverilog testbench. Is there any way to use the vhdl record type for the testbench signals? If so how do I constrain the record in systemverilog?

Or do I have to create a VHDL package that constrains the record and provides it as a type to be used in the testbench?

As HDL support varies largely between tools, I am asking about questasim (modelsim's big brother, same vendor so supposedly somewhat downward compatible) in particular.

Update

I gathered the following from the Questa SIM user manual for 10.4:

A record is mapped to a struct/packed struct (Table 9-5)
Subtypes are not mentioned in Table 9-5

I tried:

using a subtype in system verilog to connect to a port of the unconstrained type
using a subtype in system verilog to connect to a port of the unconstrained type with constraints
using a subtype in system verilog to connect to a port of the subtype
using the unconstrained type (without constraints) in system verilog to connect to a port of the unconstrained type with constraints.

Sample code:

VHDL:

library IEEE;
use IEEE.std_logic_1164.all;

package module_crosslanguage_pkg is
    type t is record
        s : std_ulogic_vector(2 downto 0);
        c : std_logic_vector;
    end record;

    subtype t_s is t(c(1 downto 0));
end package;

use work.module_crosslanguage_pkg.all;

entity dummy_test is
    port(a : in t);                -- 1.
    port(a : in t(c(1 downto 0))); -- 2.
    port(a : in t_s);              -- 3.
    port(a : in t(c(1 downto 0))); -- 4.
end entity;

architecture a of dummy_test is
begin
end;

System Verilog

module modulebay_testbench();

import module_crosslanguage_pkg::*;

    t_s testsignal;
    t testsignal2;

    dummy_test u(.a(testsignal)); -- 1., 2., 3.
    dummy_test u(.a(testsignal2)); -- 4.
endmodule;

The error is always Fatal: (vsim-3362) The type of VHDL port 'a' is invalid for Verilog connection (1st connection).

This is entirely a Questasim question. See IEEE Std 1076-2008 14.2 Elaboration of a design hierarchy, paras 7 and 8 quoted): *Similarly, the means by which top-level interface objects are associated with the external environment of the hierarchy are also defined by an implementation supporting top-level interface objects. — user1155120

dave_59 dave_59 · Accepted Answer · 2016-10-21T17:40:58

Yes, see Sharing User-Defined Types in the Questa User Manual. It shows how to import packages defined in one language and use/import them in the other.

VHDL unconstrained records in system verilog testbenches

Update

1 Answers