SystemVerilog equivalent of VHDL record ports

2
votes

My VHDL entity has those two unidirectional record ports:

user2regs     : in user2regs_t;
regs2user     : out regs2user_t

Which are defined in a package as follows:

type user2regs_t is record
    status_value : std_logic_vector(31 downto 0);
end record;

type regs2user_t is record
    control_led : std_logic_vector(3 downto 0);
end record;

How do I implement the same ports/interface in a synthesizable SystemVerilog module?

1
vhdlsystem-verilog

1 Answers

5
votes

These are structures in SystemVerilog. 

typedef struct {
   logic [31:0] status_value;
   } user2regs_t

typedef struct {
   logic [3:0] control_led;
} regs2user_t;

module mod ( input user2regs_t user2regs,
             output regs2user_t regs2user);