in reference to this post How to write to two output ports from inside architecture in VHDL? I made a VHDL module using the same concept as decribed in one of its answers. His code:
entity HIER is
port (
IN1 : in bit;
OUT1, OUT2 : out bit);
end hier;
architecture HIER_IMPL of HIER is
signal temp : bit;
component BUF1 is
port (a : in bit; o : out bit);
end component;
begin
BUF2 : BUF1 port map (a => IN1, o => temp);
OUT1 <= temp;
OUT2 <= temp;
end HIER_IMPL;
His generated RTL(using xilinx 9.1i)
I made a D flip flop using the same concept of signal to drive output ports my code:
entity dfff is
Port ( D : in STD_LOGIC;
clk : in STD_LOGIC;
Q : out STD_LOGIC;
Qbar : out STD_LOGIC);
end dfff;
architecture Behavioral of dfff is
component nand_2 is
port(A:in std_logic;
B:in std_logic;
C:out std_logic);
end component;
component not_1 is
port(A:in std_logic;
B:out std_logic);
end component;
signal Z : std_logic_vector(4 downto 0);
begin
n1 : not_1 port map (D,z(0));
n2 : nand_2 port map(D,clk,z(1));
n3 : nand_2 port map(z(0),clk,z(2));
n4 : nand_2 port map(z(1),z(3),z(4));
n5 : nand_2 port map(z(2),z(4),z(3));
Q<=z(4);
Qbar<=z(3);
end Behavioral;
my generated RTL(using xilinx 9.1i):
Now MY question is that why My output ports Q and Qbar not visible in the RTL while his OUT1 and OUT2 are? I am a beginner in this field.
