How I make an output logic signal a real output pin?

Question

I am trying to take this signal : signal Fx3_bridge : std_logic_vector (1 downto 0);

To this output port: Fx3_A : out std_logic;

I also want to discard the less significant bit of my logic vector.

Answer 1

A std_logic_vector is an array. Your std_logic_vector

signal Fx3_bridge : std_logic_vector (1 downto 0);

has two elements - 1 and 0. You index arrays in VHDL using brackets, so the most significant bit (strictly speaking: the left hand element) is

Fx3_bridge(1)

So, you want something like:

Fx3_A <= Fx3_bridge(1);