I was trying to understand how we are generating verilog code out of "for" loop in chisel. Generally verilog code used to unroll body as many time as loop progress but here in chisel it's only unrolling it once.
val io = new Bundle {
val a = UInt(INPUT, 2)
val output = UInt(OUTPUT, 2)
}
io.output := UInt(0)
for(j <- 0 to 4){
io.output := io.a
}
Corresponding verilog code for the above program is :
module LutSimpleALU(
input [1:0] io_a,
output[1:0] io_output
);
assign io_output = io_a;
endmodule
it would be very helpful if someone can tell how for loop is working.