Is there a construct in Chisel to generate Verilog generate
blocks instead of unrolling Scala for-loops into very large (>100k line) output Verilog and FIRRTL files.
For example, I have the following code, that constructs a 2D lattice of MatrixElement
modules and connects their inputs and outputs.
private val mat_elems = Seq.tabulate(rows, cols) { (i, j) => {
Module(new MatrixElement(n=i, m=j))
}}
for (i <- 0 until rows; j <- 0 until cols) {
// Wavefront propagation
if (i == 0 && j != 0) {
// First row
mat_elems(i)(j).io.in <> (false.B, false.B, mat_elems(i)(j - 1).io.out)
} else if (i != 0 && j == 0) {
// First col
mat_elems(i)(j).io.in <> (false.B, mat_elems(i - 1)(j).io.out, false.B)
} else if (i >= 1 && j >= 1) {
// Internal matrix
mat_elems(i)(j).io.in <> (mat_elems(i - 1)(j - 1).io.out, mat_elems(i - 1)(j).io.out,
mat_elems(i)(j - 1).io.out)
}
}
I am looking to compile this code for values of rows
and cols
>= 256. So this matrix gets very large in size.
If I were writing this as Verilog module, I would make use of generate
blocks. However, in Chisel, since I am using the Scala loops, the entire lattice/matrix gets unrolled in the FIRRTL/Verilog outputs. Often producing >100k lines with all the _T*
wires for 512x512 lattices. This causes a whole bunch of JVM out of memory errors in the Chisel compilation and makes the VCS simulation (just parsing the files takes forever) of the output files VERY slow.
Is there any way around this? Maybe get Chisel to generate Verilog generate
blocks?