single-cycle MIPS timeing questions

Question

I read the book "Computer Organiztion and Design", in chapter 4, it describes a single-cycle MIPS machine. however, I have several doubles about it.

If the data memory and the instruction memory in the design are SRAMs, how can any instructions be finished in a signle clock cycle . Take a load instruction as an example, I think the single-cycle MIPS design still has to go through the following stages. only the ID and EXE stage are merged.

|   1    |   2    |   3    |   4  |
|   WB   |        |        |      |
|        |   IF   |        |      |     
|        |        | ID\EXE |      | 
         |        |        |  MEM |

if the data memory is updated at the negedge clock, the ID, EXE and MEM stage can be merged, but there are still three stages left.

Can any one explain how the "Single-Cycle" works? Thanks!

In an unpipelined (single cycle) processor, the processor cycle time can be longer than the memory cycle time. — Paul A. Clayton
But if both the memory and registers only update at the posedge clock, no matter how long the processor cycle time is, it seems impossible to finish a LD instruction since it read the memory and write the register. — JIE

Tayyar R Tayyar R · Accepted Answer · 2014-07-19T20:22:40

The single cycle processor that you read about in chapter 4 is a slight oversimplification over what is implementable in reality. They don't show some of the tricky details. For instance one timing assumption you could make is to assume that your memory reads are combinational and mempory writes take 1 positive edge to complete, i.e. simiar to the register file. So in that case when the clock edge arrives you have your IF stage populated with an instruction. Then for the duration of that cycle, you decode and execute the instruciton and writeback happens on the next clock edge. In case it is a data store same thing is true, the memory will be written on the next clock edge. In case of loads, you are assuming combinational memory read, so your data will arrive before the clock edge and on the edge it will be written to the register file.

Now, this is not the best way to implement this and you have to make several assumptions. In a slightly more realistic unpipelined processor you could have a stall signal that would roll over to the next cycle if you are waiting for the memory request. So you can imagine you would have a Stall_on_IF signal and Stall_on_LD signal that would tell you to stall this cycle until your instruction/data arrives. When they do arrive, you latch them and continue execution next cycle.

single-cycle MIPS timeing questions

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