Why isn't MIPS BLT instruction implemented in hardware?

2
votes

I'd like to ask why the BLT instruction is not a part of MIPS ISA. Instead they actually make it a pseudo-instruction for assembly programmers. I just couldn't recognize the difference between BLT and BLTZ (which is a part of MIPS ISA) from hardware implementation point of view.

By the way the book "Computer Organization and Design" says :

Heeding von Neumann's warning about the simplicity of the "equipment" the MIPS architecture doesn't include branch on less than because it's too complicated either it would stretch the clock cycle time or it would take extra clock cycles per instruction, the two faster instructions are more useful.

But I still have no idea why those might happen.

1
branchmipshardwarecpu-architecture

1 Answers

5
votes

It's much easier to compare with zero

Because less than zero is really just a sign bit check while less than is

  • a subtract and then jump based on the sign bit of the result, or
  • a lexicographic comparison of the binary representations of the input values

Either way is far more complex than a single bit check, therefore BLTZ is much faster. Similarly, >= 0 also needs only 1 sign bit check. <= 0 and > 0 need another zero check but it's rather trivial.

In fact, it's not common that an architecture supports jump-and-compare between two values directly in a single instruction, although most will have jumps based on the value in relation to 0. Even CISC architectures like x86 require the user to compare and then jump