1
votes

So on https://en.wikipedia.org/wiki/Cycles_per_instruction it says:

For the multi-cycle MIPS, there are 5 types of instructions:

  • Load (5 cycles)
  • Store (4 cycles)
  • R-type (4 cycles)
  • Branch (3 cycles)
  • Jump (3 cycles)

I'm unsure how many cycles the instruction 'addi' takes since there's no specific mention of it.

'add' is a R-type instruction and therefore takes 4 cycles, so my best guess would be that 'addi' (I-type instruction) also takes 4. Could someone please confirm or correct my guess?

1
in a purely academic/theoretically ideal world, sure. in the real world it is not deterministic in that way.old_timer

1 Answers

0
votes

If you are referring to the standard ideal 5-stage MIPS pipeline, then yes "ADDI" would also take 4 cycles to complete.

The only difference between ADD and ADDI is that ADDI works on an immediate value instead of using the third register. This value is available before the Execute stage of the pipeline hence there are no reasons for the instruction to take more than 4 cycles.