Verilog design - input is "unused" warning

Question

When attempting to synthesize a Verilog design (I want to generate a schematic), I get the following warning:

Synthesizing Unit <rising>.
  Related source file is "C:\PPM\PPM_encoder\detectors.v".
  WARNING:Xst:647 - Input <in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
  Summary:
    no macro.
Unit <rising> synthesized.

The relevant module is simply:

module rising (in, out);
output out;
input in;

not #(2,3) (ininv, in);
and #(2,3) (out, in, ininv);

endmodule

And I call it in several different locations, including:

rising startdetect(
  .in(start),
  .out(or01a));

When I complete the synthesis and then choose to "View schematic", only one component is actually present. Expanding that component, I see only the output being connected to ground, which is the initial condition. Nothing else is present. This is with my testbench as my "top module".

When I select my actual main project (below the testbench, it's called ppmencode) as the top module, I get those same warnings, plus additional warnings for every single module instance:

WARNING:Xst:1290 - Hierarchical block <startdetect> is unconnected in block <ppmencode>.
  It will be removed from the design.

What is the cause of these two warnings, and how can I fix them and be able to generate a correct schematic?

Edited to add: The whole thing simulates perfectly, it's just when trying to make a schematic (to try to explain this thing that I just made to my team) that I run into problems. This image shows the schematic that I get.

Answer 1

It's not enough to have a signal named as an input to a module...it needs to actually be connected to a pin on the FPGA. On the other hand, your rising module is taking the AND of the input and its complement...the synthesizer might have figured out a way to simplify that logic that is contrary to your wishes.

Answer 2

Synthesis is optimizing all the logic out because it ignores the delays. Functionally you have in & ~in which is always 0. What you intend is a pulse generator. One way to achieve this is to use the dont_touch attribute, which tell the synthesizer that it must keep a particular module instantiation in the design. See this Properties Reference Guide for more.

module rising (in, out);
output out;
input in;

(* DONT_TOUCH = "TRUE" *)
not #(2,3) (ininv, in);
and #(2,3) (out, in, ininv);

endmodule

Be warned that even with the dont_touch your synthesize result may not match simulation. Synthesis ignores the artificial timing in your netlist. The actual pulse width could be longer, more likely shorter or to small to be registered. Check your standard cell library and look for a delay cell to apply to ininv, this will increase the pulse width. The library may already have a pulse generator cell already defined.