Is there any recommended way to automate module port connection?

6
votes

I'm trying to understand or research about the best practices of ASIC design in verilog. I'm working on a medium size block with ~20 sub modules (each ~1000 lines of code). It's a painstaking job to manually instantiate all the sub-module and do port connection to create top level RTL.

I want to write a script to automate this. As long as we can define the input/outputs of all the sub-modules and how each sub-modules are connected with each other, it shouldn't be super hard to auto-generate the top level. I don't have enough expertise in design automation though. I was wondering if anyone can give me some pointers about how to get started.

  • Is there any open source tool to achieve what I'm trying to do? I didn't find any so far.
  • Is there any standardize way to generate synthesizable code of this sort?

I'll highly appreciate any sort of input or advice.

1
automationverilogsystem-verilog
You could use .* implicit port connections if the patent module has the same variables as port names in submodule. But use it carefully. – rahulcodesinverilog
You can make perl script and inputs files of modules and generate one top file where you can do some stings logics and instantiate sub-modules in top file. Try with small module and then expand it with your requirement. You can not ask for direct script but you can, but it is possible. – Prakash Darji
Not an automatic solution, but here's what I often do. Paste in the submodule definition (ie module #(...) (input logic ..., output logic ...); and then add the instance name and delete all the port directions and types. Now use the macro recording function on your editor to do this: CUT . PASTE ( PASTE ). Then double click each port name to highlight it and then execute the macro. That changes some_name to .some_name(some_name). If the port and connection name are the same, then job done. If not, it's easy to do a bit more double clicking, copying and pasting. I don't like .*. – Matthew Taylor

1 Answers

5
votes

Depending on what text editor you're using, you might be able to use some pre-existing tools. There is an add-on for Emacs that supports auto-instantiating and connecting signals, assuming that you follow certain naming conventions:

http://www.veripool.org/wiki/verilog-mode/Verilog-mode_veritedium

For the vim users out there, there are a couple of plugins that allow using the Emacs script, such as this one:

http://www.vim.org/scripts/script.php?script_id=1875