Why am I getting this parenthesis error in Verilog?

Question

I am trying to initiate a module in a top level in Verilog (beginner). Here is the top Level code:

module top(

//////////// SEG7 //////////
output           [7:0]      HEX0,
output           [7:0]      HEX1,
output           [7:0]      HEX2,
output           [7:0]      HEX3,
output           [7:0]      HEX4,
output           [7:0]      HEX5,

//////////// LED //////////
output           [9:0]      LEDR,

//////////// SW //////////
input            [1:0]      SW);
always@(SW) begin



testgen test(.select[1](SW[1]), .select[0](SW[0]), data0[3:0], data1    [3:0], data2[3:0], data2[3:0]);



end

endmodule

Here is testgen (the module I'm trying to initiate

module testgen (
input      [1:0] select,
output reg [3:0] data0,
output reg [3:0] data1,
output reg [3:0] data2,
output reg [3:0] data3
);

always @(*) begin
  case (select)
     2'b00: begin
        data0 = 4'b0011;    // 3
        data1 = 4'b0010;    // 2
        data2 = 4'b0001;    // 1
        data3 = 4'b0000;    // 0
     end
     2'b01: begin
        data0 = 4'b1010;    // A
        data1 = 4'b1100;    // C
        data2 = 4'b1110;    // E
        data3 = 4'b1111;    // F
     end
     2'b10: begin
        data0 = 4'b0111;    // 7
        data1 = 4'b0001;    // 1
        data2 = 4'b0000;    // 0
        data3 = 4'b1010;    // A
     end
     2'b11: begin
        data0 = 4'b0101;    // 5
        data1 = 4'b1111;    // F
        data2 = 4'b1100;    // C
        data3 = 4'b0010;    // 2
     end
     default: begin
        data0 = 4'b0000;    // 0 should never be selected
        data1 = 4'b0000;    // 0 should never be selected
        data2 = 4'b0000;    // 0 should never be selected
        data3 = 4'b0000;    // 0 should never be selected
     end
  endcase
end

endmodule

There's a bunch of other modules I want to incorporate in the top level, but I just want to know why I'm getting the following error

Error (10170): Verilog HDL syntax error at top.v(29) near text: "[";    expecting "(".

Am I instantiating incorrectly? Why is this happening? Line 29 is the line where I instantiate testgen. Any help would be appreciated, thanks!

Unn Unn · Accepted Answer · 2018-04-25T22:57:52

There two major issues with your code that I can see. First is you are instantiating a module in an always block. Modules should always be instantiated on a "top" level, ie not in a procedural block like always or assign but just in a module's body. Remember, modules are not functions and are not called like functions but instantiated. Second, you cannot assign ports using the .port[index](var) syntax, you need to assign an entire port to a single variable. To do what you are trying to do, you should just pass in your SW variable to your select port of testgen like so (also, use that explicit assignment for all variables):

testgen test(.select(SW), // Just connect these directly, will connect SW[0] to select[0], SW[1] to select[1]
             .data0(data0), // Use .port explicit connection for all variables
             .data1(data1), // Minor issue, the code you provided doesnt define data0-data2 in the top module, be careful of implicit declaration
             .data2(data2), // Use "`default_nettype none" to avoid these issues
             .data3(data2)); // You use data2 here and not data3, its unclear if that was intentional

Why am I getting this parenthesis error in Verilog?

1 Answers