Verilog XST ignores hard coded input values

Question

I run into a bit of an issue with ports in Verilog. In order to test my module, I created a top module with just wires as inputs and hardcoded some of the inputs (vector) to the core module. The thing I do not get is that XST shows those inputs to the core (which I am driving with the hardcoded values) as connected to ground. The image is below.

Some where else in the Core, it disconnects some blocks from inside of the core. I do not know how this second issue is linked with the input being hardcoded. Does this mean that inputs cannot be hardcoded at the top? Or do I have to disconnect all the sub blocks that use the inputs and manually provide the same hardcode for each of them (which I think is redundant)?

I just see red wires, I don't see any ground connections. Anyway that is not important: show us the code. Beware that logic optimization can lead to unexpected (which is not the same as wrong) results. By the way its is preferred to include pictures in the question. — Oldfart

Barry Moss Barry Moss · Accepted Answer · 2018-09-21T02:18:53

Hard coding inputs to a block will definitely result in logic optimization. In some cases this may result in the removal of entire blocks of logic because hard coded inputs caused the output of those blocks to be fixed values. During synthesis, the hard coded values are propagated through the design and the resulting logic is minimized. In the most simple example, hard coding the input to an inverter results in the inverted being removed and replaced with a hard coded output with an opposite value to the hard coded input. In your example, hard coding the CLK to any value, RSTn to 0, START to 0 would probably wipe out most of the internal logic of CORE because you would effectively disable the block. Similarly, hard coding some of the vectors might cause large sections of logic to be optimized away.

Verilog XST ignores hard coded input values

1 Answers