Implementing PIPO in verilog

0
votes

I am looking to implement a 32-bit Parallel in-Parallel out in verilog HDL. Here is the code I have written...

module pipo(input_seq, answer,reset, clock);
   input [31:0] input_seq;
   input        reset,clock;
   output [31:0] answer;

   always @ (reset)
     begin
        if(!reset)
          begin
             answer[31:0]<=1'b0;
          end
     end

   always @ (posedge clock)
     begin
        answer[31:1]<=input_seq[30:0];  
     end

endmodule

However this leads to the following error log( using iverilog):

pipo.v:10: error: answer['sd31:'sd0] is not a valid l-value in pipo.
pipo.v:4:      : answer['sd31:'sd0] is declared here as wire.
pipo.v:16: error: answer['sd31:'sd1] is not a valid l-value in pipo.
pipo.v:4:      : answer['sd31:'sd1] is declared here as wire.
Elaboration failed

What are the problems?

2
verilogicarus
You should not split the reset logic of a register and the clocking logic of a register into seperate blocks. You should have one block always @(posedge clock or negedge reset). In your design the clocking block will still be executed if the clock toggles while reset is asserted, which is not the correct way to model a flip flop. – Tim

2 Answers

5
votes

You are using answer as a register, but it's declared as a wire. Wire is something which connects two points, and thus does not have any driving strength. On the other hand reg can store value and drive strength.

Change declaration of answer to reg and it should help.

output reg [31:0] answer;
-1
votes

I recommend you that when you are describing combo logic, use blocking assignment.

always @ (reset)
   begin
     if(!reset)
       begin
         answer[31:0]=1'b0; //blocking assignment
       end
   end

About this block:

always @ (posedge clock)
  begin
    answer[31:1]<=input_seq[30:0];  
  end

You can fix the errors by making the output output reg [31:0] answer and this will let you assign an output in an always block.