I'm implementing a module to count number of '1's in an input vector and cannot fix the inferring latches error.
Warning (10240): Verilog HDL Always Construct warning at top_module.v(15): inferring latch(es) for variable "count", which holds its previous value in one or more paths through the always construct File: /var/www/verilog/work/vlgaaQTZu_dir/top_module.v Line: 15 Warning (10240): Verilog HDL Always Construct warning at top_module.v(15): inferring latch(es) for variable "mask", which holds its previous value in one or more paths through the always construct File: /var/www/verilog/work/vlgaaQTZu_dir/top_module.v Line: 15
I've tried to add an else expression in the for loop after if statement, and also add an initial statement to initialize the value of count and mask.
module top_module(
input [254:0] in,
output [7:0] out );
wire [7:0]count;
wire [254:0]mask;
initial begin
count = 8'h0;
mask = 255'h1;
end
always @(*)
begin
for(int i = 0; i < 255; i = i + 1)
begin
if(in & mask)
begin
count = count + 1;
mask = mask << 1;
end
else
begin
count = count;
mask = mask;
end
end
out = count;
end
endmodule
I failed to pass the complying.