NAND basic cell using structural vhdl

Question

I have a problem designing memory circuits in VHDL. I am trying to figure out a soultion to the following prompt:

Create a NAND basic cell in the Xilinx tools using structural VHDL methods. Add a 1ns gate delay to both NAND gates (for both rising and falling transitions). Label inputs S and R and the outputs Q and QN as appropriate. Create a VHDL test bench to simulate the circuit, driving the inputs as specified below.

De-assert both inputs at the start of the simulation. At 100ns, asset S. At 200ns, de-assert S. At 300ns, assert R. At 400ns, de-assert R. At 500ns, assert both inputs. At 600ns, de-assert both inputs. At 700ns, assert both inputs.

An undefined output
A set operation
A reset operation
A ‘0’ being stored in memory
A ‘1’ being stored in memory
A state where the Q and QN outputs are both driven to the same value
A metastable state

If i could get just a basic example of what the code will look like i can design a NOR circuit also (That is the actual problem i wish to solve) but a NAND example will be sufficient.

I have tried using this model for the structural code

 import std_logic from the IEEE library
    library ieee;
    use ieee.std_logic_1164.all;

    --ENTITY DECLARATION: name, inputs, outputs
    entity nandGate is
       port( A, B : in std_logic;
                F : out std_logic);
    end nandGate;

    --FUNCTIONAL DESCRIPTION: how the NAND Gate works
    architecture func of nandGate is 
    begin
       F <= A nand B;
    end func;

and this model for the test bench 



 architecture tb of nandGate_tb is
       --pass nandGate entity to the testbench as component 
       component nandGate is
       port( A, B : in std_logic;
                F : out std_logic);
       end component;

       signal  inA, inB, outF : std_logic;
    begin
       --map the testbench signals to the ports of the nandGate
       mapping: nandGate port map(inA, inB, outF);

       process
          --variable to track errors
          variable errCnt : integer := 0;
       begin
          --TEST 1
          inA <= '0';
          inB <= '0';
          wait for 15 ns;
          assert(outF = '1')  report "Error 1" severity error;
          if(outF /= '1') then
             errCnt := errCnt + 1;
          end if;

          --TEST 2
          inA <= '0';
          inB <= '1';
          wait for 15 ns;
          assert(outF = '1')  report "Error 2" severity error;
          if(outF /= '1') then
             errCnt := errCnt + 1;
          end if;

          --TEST 3
          inA <= '1';
          inB <= '1';
          wait for 15 ns;
          assert(outF = '0')  report "Error 3" severity error;
          if(outF /= '0') then
             errCnt := errCnt + 1;
          end if;

          -------------- SUMMARY -------------
          if(errCnt = 0) then
             assert false report "Good!"  severity note;
          else
             assert true report "Error!"  severity error;
          end if;

       end process;
    end tb;

The instructions are garbled. They start out talking about a NAND cell (not a NAND gate), then (without ever mentioning the term) switch to talking about an S-R Latch - which is presumably what they mean by "NAND cell", as it is usually built out of NAND gates. Researching "S-R Latch" should help you. — user_1818839
Have you just copied your entire homework assignment to Stack Overflow?? If you don't understand something specific, ask, clearly. If you want someone to do your homework for you, you should look elsewhere. — EML

QuantumRipple QuantumRipple · Accepted Answer · 2013-10-07T03:36:16

The question is asking you to create an SR latch (called NAND basic cell in the instructions) from a cross-coupled pair of NAND gates. The delay mentioned would be in the logic equation for the functional description of the NAND gate.

The following is a structural VHDL model of an SR latch made of two NAND gates:

entity nandCell is
   port( S, R  : in std_logic; --S and R are active low
         Q, QN : out std_logic);
end nandCell;

architecture structural of nandCell is 
   --NAND gate component declaration
   signal Qint, QNint : std_logic; --these internal signals are required to be able to read the "outputs"
begin
   n1 : nandGate port map(S, QNint, Qint);
   n2 : nandGate port map(R, Qint, QNint);
   Q <= Qint;
   QN <= QNint;
end structural;

NAND basic cell using structural vhdl

1 Answers