VHDL - AND operation between vector and bit

1
votes

i'm starting in VHDL, and I have a problem trying add a enable to a port. I have an output vector of 8 bits, and I want to put a value if the "Enable"bit input is '1'. Else, put a '0' in the vector.

I can make:

out(0) <= '0' AND Enable;
out(1) <= '0' AND Enable;
out(2) <= '1' AND Enable;
out(3) <= '0' AND Enable;
out(4) <= '1' AND Enable;
...
out(7) <= '0' AND Enable;

There are a easy way to make this? I'm thinking like: out <= "01010100" AND Enable; but it doesn't work...

I can use an "if", but i prefer use this way to understand how to do it.

2
vhdl

2 Answers

4
votes

And it with another vector of the same size, initialised with (others => Enable)

A more complete example : 

subtype Data_Word is std_logic_vector(7 downto 0);

signal Out, Value, Mask : Data_Word;
...
Mask <= (others => Enable);
Out <= Value and Mask;

or perhaps simply

Out <= Value and (Out'Range => Enable);
4
votes

A tidy way to do this is with a conditional signal assignment:

Out <= Value when Enable = '1' else (others=>'0');

...as a bonus, you can assign any value you want (even a different signal vector) when Enable is low.