How to make a simple 4 bit parity checker in VHDL?

1
votes

I am trying to learn VHDL and I'm trying to make 4-bit parity checker. The idea is that the bits come from one input line (one bit per clock pulse) and the checker should find out if there is odd number of 1s in the 4-bit sequence (i.e 1011 , 0100 , etc.) and send an error output(e.g error flag: error <=´1´) if there is.

Would someone give me an example how it´s done, so that I can study it?

I have tried searching the web, but all the discussions I found were related to something way more complicated and I could not understand them.

4
vhdl
PS. I am simulating it with xilinx ISE-enviroment using XC3S200 device - user1054844
what would you get if you added the bits to an accumulator as they come in? - Jim Rhodes
It is just an "easy" exorcise, so if there isn´t an error the input bits don´t really matter. I have tried to make a while loop with two states (odd, even) and if I end up in the odd state output error <=´1´ , but I could not get it working... - user1054844

4 Answers

5
votes

VHDL 2008 standard offers a new xor operator to perform this operation. Much more simple than the traditional solution offered by Aaron.

signal Data : std_logic_vector(3 downto 0) ;
signal Parity : std_logic ;
. . .
Parity <= xor Data ;
3
votes

This assumes "invec" is your input std_logic_vector:

parity <= invec(3) xor invec(2) xor invec(1) xor invec(0);

If it got any larger than 4 inputs, a loop would probably be best:

variable parity_v : std_logic := '0';
for i in invec'range loop
  parity_v := parity_v xor invec(i);
end loop;
parity <= parity_v;

That loop would be converted into the proper LUT values at synthesis time.

(I did this from memory; may be slight syntax issues.)

0
votes

small syntax error in the code. should remove ":" after loop.

0
votes
library ieee;
use ieee.std_logic_1164.all;

entity bus_parity is

    generic(
        WPARIN : integer := 8
    );

    port(
        parity_in  : in std_logic_vector(WPARIN-1 downto 0);
        parity_out : out std_logic
    );
end entity;


architecture rtl of bus_parity is
begin

process(parity_in) 
   variable i :     integer;
   variable result: std_logic;
begin

    result := '0';

    for i in parity_in'range loop
        result := result xor parity_in(i);
    end loop;

    parity_out <= result;
end process;


end architecture;

Or in Verilog:

`timescale 1ns/10ps
`default_nettype none

module bus_parity #(
    parameter WPARIN = 8
) (
    input  wire [WPARIN-1:0] parity_in,
    output reg               parity_out
);

always @* begin : parity
    integer i;
    reg     result;

    result = 1'b0;
    for(i=0; i < WPARIN-1; i=i+1) begin
        result = result ^ parity_in[i];
    end

    parity_out = result;
end

endmodule

`default_nettype wire