VHDL - GHDL Initialise std_logic_vector with smaller bit length

Question

I have a signal dataIn : std_logic_vector ( 15 downto 0);

I want to give an input less than 16-bits for example dataIn <= x"000a" and those bits occupy the most significant bits and the rest to be zero. In verilog you can do that very easy but in VHDL you get the error:

"string length does not match that of the anonymous integer subtype defined t... ".

I know that if you use 16x"bit_string" solves the problem but this is only for VHDL-2008 and ghdl doesn't support yet VHDL-2008.

Are there any method for IEEE Std 1076-2002?

ghdl actually does support VHDL2008 (in my opinion even more complete than most of the commercial simulators). Download latest version and try the --std=08 command line switch. — mfro
Your example dataIn <= x"000a" supplies a simple signal assignment waveform expression that has a length of 16. E.g. IEEE Std 1076-2002 13.7 Bit string literals "If the base specifier is 'O' (respectively 'X'), the value of the bit string literal is the sequence obtained by replacing each extended digit in the bit_value by a sequence consisting of the three (respectively four) values representing that extended digit taken from the character literals '0' and '1';..." (which is easier to read for your purposes than -2008 15.8 Bit string literals, expanded bit value). Try a different example. — user1155120

andrsmllr andrsmllr · Accepted Answer · 2019-05-19T18:17:23

For VHDL-87/93/2002 you could use the resize function from the numeric_std package.

library ieee;
use ieee.numeric_std.all;
...
constant FOO : std_logic_vector(2 downto 0) := "010";
signal dataIn : std_logic_vector(15 downto 0) := std_logic_vector(resize(unsigned(FOO), 16));

Note that the resize function is only defined for types signed and unsigned.
If you want the short bit string to be placed into the MSBs you may need to use the 'reverse_order attribute.

Often you will find it easier to define a dedicated function which encapsulates more complicated initializations.

constant FOO : std_logic_vector(2 downto 0) := "010";

function init_dataIn (bar : std_logic_vector; len : integer) return std_logic_vector is
begin
  return bar & (len - bar'length - 1 downto 0 => '0');
end function init_dataIn;

signal dataIn : std_logic_vector(15 downto 0) := init_dataIn(FOO, 16);

VHDL - GHDL Initialise std_logic_vector with smaller bit length

1 Answers