VHDL Simulation Timing Behaviour

0
votes

I'm trying to write some VHDL code that simply feeds sequential bits from a std_logic_vector into a model of an FSM. However, the bits don't seem to be updating correctly. To try figure out the issue, I have the following code, where instead of getting a bit out of a vector, I'm just toggling the signal x (the same place I'd be getting a bit out).

    clk <= NOT clk after 10 ns;
    process(clk) 
        begin
            if count = 8 then
                assert false report "Simulation ended" severity failure;
            elsif (clk = '1') then
                x <= test1(count);
                count <= count + 1;
            end if;         
    end process;

EDIT: It appears I was confused.I've put it back to trying to take bit by bit out of the vector. This is the output. I would have thought that on when count is 1, x would take on the value of test1(1) which is a 1.

enter image description here

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vhdl
What do you mean by "... count and x are not updating at the same time, i.e. on the rising edge of my clock signal." ? From the waveform, and as expected by the code, the count and x are indeed updated at the rising edge of clk. – Morten Zilmer
x,count are updated on the rising edge. – drahnr
Yes sorry, I'd got my clock line confused. I've updated the question with what it outputs when I try get the bits out of the vector. – chris
Post edit, the code matches the waveform. when count is 1 x is assigned test(1) on the next rising clock edge. test(1) is '0'. To get it to start with the MSB (left element of test) you need count down from 7 to 0 or use the compliment index value to count (7 - count), which is the equivalent of the inverted outputs of a 3 bit counter. – user1155120
Answer your own question and accept it or close the question. We have lots of zombie questions. – user1155120

1 Answers

1
votes

As David points out in the comments, the code is working fine. The issue was my ignorance of bit order in the std_logic_vector.