Best VHDL design practice

Question

Question about best VHDL design practice.

When designing state machines, should I use a signal within the Architecture or use an variable. I have until now used variables, since they are "kinda" private to the process, and IMHO makes good sense because they should not be accesses outside the process. But is this good design practice?

type state_type is (s0,s1);  
signal state : state_type := s0;  

A : process(clk)
begin   
  if rising_edge(clk) then  
    case state is  
.....  
    end case;  
  end if;
end process;  

--This process uses a variable  
B : process(clk)  
  type state_type is (s0,s1);  
  variable state : state_type := s0;  
begin  
  if rising_edge(clk) then  
    case state is  
      .....  
    end case;  
  end if;
end process;  

Answer 1

I prefer to use signals. The reason is that it allows the design to be split between multiple processes. One process can worry about how the state machine moves from state to state, and other processes can contain logic that is dependent on the state.

Doing it this way means you can have multiple simple processes that do one thing each. Using variables, everything has to go into the one process and that can become unwieldy.

It's a stylistic choice though.

Answer 2

I always use variables unless I need to communicate some value to another process. Because that's what signals are for.

Another potential benefit (or alternatively, something to watch as a violation of your coding standards!) of "localising the state variable" is that you can call the type and the variable state_type and state in two state machines in the same entity without them clashing...

Answer 3

For synthesis, I almost exclusively use signals.

Why?

• Signals seem to be more universally understood.
• Code clarity. Signals are all updated once, at the same time. Mixing variables and signals can be (potentially) confusing because you must remember that variable assignment takes effect immediately, whereas subsequent signal assignment implies priority. The value of a signal will never change during the same execution of a process.
• Lower risk of deep logic paths. Inexperienced designers may be tempted to use variables like a C program, which would result in logic that will not meet timing goals.

Why Not?

• Large designs end up with very long lists of signals and can be difficult to find the signal types/sizes/etc. Typically this only occurs for wrappers of the largest blocks in a design, and/or a design top level.

For testbench, I use variables and signals, depending on the use.

Answer 4

If the signal in this case it's not needed as an input or output of your process is a better use to use variables because when you're building the architecture you will need to assign a signal to the output of the module, and if it won't be used, it's not necessary to create the signal and spend more memory for something you won't use to connect to another module of your architecture.