VHDL. There are 2 loadless signals in this design

Question

I just started VHDL coding and i uses XILINX Artix-7/NEXYS 4 to practice. I only want to design the seven segment display and let it dsiplay the numbers from 0 to 9. My English is not very good, please forgive me, I tried to express my question.

In my code,i split the architecture into four steps. First,i down the clk(100MHZ) to 1hz. Second,i use counter to count the number from 0 to 9 then use the double dabble algorithm separate the number.Last,i wrote a BCD to 7 segment decoder and choose the first anode.

The problem is that warning appears when i was implement circuits,even though the synthesize is fine(but the RTL show that signal has not connect obviously). The problem seems to between the double dabble algorithm and counter? (since it has wrong after add this code) I really want to know how could i solve this problem?And when will this warning appear?Maybe my code have big wrong?

WARNING:Par:288 - The signal clk_IBUF has no load. PAR will not attempt to route this signal.

Finished initial Timing Analysis. WARNING:Par:288 - The signal btnD_IBUF has no load. PAR will not attempt to route this signal.

WARNING:Par:283 - There are 2 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

By the way,I know there has many ways to achieve my goal,but i really want to know what a wrong with this. If any one can help me,THANKS A LOT.

Here is my code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.all;
use IEEE.numeric_std.all;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
    Port ( clk : in  STD_LOGIC;
           btnD : in  STD_LOGIC;
           an : out  STD_LOGIC_VECTOR (7 downto 0);
           seg : out  STD_LOGIC_VECTOR (6 downto 0));
end top;

architecture Behavioral of top is

signal clk_1hz_s : STD_LOGIC := '1';
signal clk_1hz : STD_LOGIC;
signal counter_clock : integer range 0 to 5000000 := 0;
signal sec_turth : STD_LOGIC_VECTOR (7 downto 0);
signal sec_1 : STD_LOGIC_VECTOR (3 downto 0);

begin

--new clk--
process(clk,btnD)
begin

    if (clk' event and clk='1') then
        if (btnD = '1') then
            counter_clock <= 0;
            clk_1hz_s <= '1';
        elsif (counter_clock = 5000000 - 1 ) then
            counter_clock <= 0;
            clk_1hz_s <= NOT(clk_1hz_s);
        else 
            counter_clock <= counter_clock + 1;
        end if;
    end if;
        
end process;
clk_1hz <= clk_1hz_s;

--counter--

process(clk_1hz)

variable sec :integer range 0 to 9 :=0;

begin

    if (clk_1hz' event and clk_1hz='1') then
        if sec > 8 then
            sec := 0;
        else
            sec := sec + 1;
        end if;
    end if;
    
sec_turth <= STD_LOGIC_VECTOR(to_unsigned(sec,8)(7 downto 0));
end process;

--double dabble algorithm--

process(sec_turth)

variable temp_sec : STD_LOGIC_VECTOR (7 downto 0);
variable bcd_sec : unsigned (7 downto 0):= (others => '0');

begin

temp_sec := sec_turth;
bcd_sec := (others => '0');

    for i in 0 to 7 loop

    if bcd_sec(3 downto 0) > 4 then
        bcd_sec(3 downto 0) := bcd_sec(3 downto 0) + 3;
    end if;
    
--  if bcd_sec(7 downto 4) > 4 then
--      bcd_sec(7 downto 4) := bcd_sec(7 downto 4) + 3;
--  end if;
    
    bcd_sec := bcd_sec(7 downto 1) & temp_sec(7);
    temp_sec := temp_sec(7 downto 1) & '0';
    
    end loop;

sec_1 <= STD_LOGIC_VECTOR(bcd_sec(3 downto 0));
--sec_2 <= STD_LOGIC_VECTOR(bcd_sec(7 downto 4));

end process;

--decoder--

with sec_1  select
    seg <= "1000000" when "0000",--0
             "1111001" when "0001",--1
             "0100100" when "0010",--2
             "0110000" when "0011",--3
             "0011001" when "0100",--4
             "0010010" when "0101",--5
             "0000010" when "0110",--6
             "1011000" when "0111",--7
             "0000000" when "1000",--8
             "0011000" when "1001",--9
             "0001110" when "1111",--F
             "1111111" when others;--close all
             
an <= "11111110";--choose the first anode

end Behavioral;

Answer 1

The warnings mean that in your code both inputs don't influence any output and thus are not worth being connected to any internal component.

Please get more familiar with the concept of variables. Especially with the sec-counter process, you should know that you can't assume that the variable keeps its value saved between two process runs, i.e. each rising edge on clk_1hz resets the variable sec. Better declare it as a signal as you do with counter_clock. Then you would of course also need a reset routine inside the counter process:

-- In the architecture header:
signal current_value: integer range 0 to 9;

-- one-digit counter --
process(clk_1hz)
begin
    if (clk_1hz'event and clk_1hz='1') then
        if (btnD = '1') then
            current_value <= 0;
        elsif current_value > 8 then
            current_value <= 0;
        else
            current_value <= current_value + 1;
        end if;
    end if;
end process;
-- I assume, you really need 8 bits here:
sec_turth <= STD_LOGIC_VECTOR(to_unsigned(current_value,8));

For a single-digit number between 0 and 9, your double dabble algorithm with all its variables is unnecessary since the values are already present in BCD. If I remove that process and simply connect lower 4 bits of sec_turth to sec_1 then the warnings disappear and I can view the schematic:

sec_1 <= sec_turth(3 downto 0);

Some other issues:

Your clock divider process is defined to be sensitive to clk and btnD inputs. This is usually the case for asynchronous reset behavior which is not implemented inside the process. If you want an asynchronous reset, do something like this:

clk_div: process(clk,btnD)
begin
    if btnD = '1' then
       -- do the reset
        counter_clock <= 0;
        clk_1hz_s <= '1';
    elsif clk'event and clk = '1' then
        -- do the synchronous operations
        if (counter_clock = 5000000 - 1 ) then
            counter_clock <= 0;
            clk_1hz_s <= NOT(clk_1hz_s);
        else 
            counter_clock <= counter_clock + 1;
        end if;
    end if;
end process clk_div;

If that should be a clock synchronous reset, please remove btnD from the sensitivity list as I did in the first code listing.

Also, I've seen that you have a space after the tick ' in the clk'event attribute that at least makes the code highlighted differently than without the space. Correct that and you might get rid of the clk-related warning. Edit: No, if the variables are removed then the space does not matter.

Hope I could help, please let me know if I can improve the answer!