What is the equivalent statement of this VHDL assignment?

0
votes

The VHDL code is:

next_x(7 downto 0) <= rec_data;

What does this line do? What is the equivalent statement? This line is within a process and is executed when condition_1 is true.

My guess is that this statement will update next_x?

Can someone please explain the statement and find the equivalent, if any?

Thanks.

1
vhdl
The equivalent statement in what? - Paul S

1 Answers

2
votes

Since this is a signal assignment, it schedules next_x to have the value of rec_data after the process completes. The biggest caveat to be aware of is that a subsequent read of signal next_x in the process where this change is scheduled will return the old value of this signal -- the change has not taken effect yet. You can think of it as being executed concurrently with all other signal assignments in the process, but multiple assignments of the same signal are allowed and only the last will take effect.

On the other hand, variable assignments take effect immediately, so changes are visible by all subsequent statements in the process, much like imperative programming languages.

The equivalent variable assignment would be next_x(7 downto 0) := rec_data;, but next_x must then be a variable, not a signal.

Here is a good summary of signal versus variable assignment.